• Circuit construction task (Task 2): Verify the functionality of a given circuit described in task 2
via circuit construction, which also include completing parts of the given circuit to achieve the required
functionality. Submission for this part includes a circuit schematic, a photo of the constructed circuit and
your student ID card, and a video showing the operation of the circuit via the specified test cases.
Submission is a single .zip file to Blackboard as detailed in the submission section of this document.
Task 1 (Design Task, 12 marks)
Consider the 4-input Boolean function F = f(A,B,C,D) defined in terms of four Boolean parametersW,X, Y, Z
by the following procedure:
• Compute the arithmetic expression E =W ·A+X ·B + Y ·C +Z ·D, where + and · are addition and
multiplication (not logical AND and OR), respectively.
• Express E in unsigned binary
• Return the least significant (rightmost) bit of E as the output of F = f(A,B,C,D).
For example, if (W,X, Y, Z) = (0, 1, 0, 1), we compute f(1, 1, 1, 1) as
• E = 0 · 1 + 1 · 1 + 0 · 1 + 1 · 1 = 2,
• E = 102,
• F = f(1, 1, 1, 1) = 0.
For this question, let (W,X, Y, Z) be defined by the last digit of your 8-digit student number as shown below.
Last digit of 8-digit student number Choice for (W,X, Y, Z)
0,1,2 (0, 1, 1, 1)
3,4,5 (1, 0, 1, 1)
6,7 (1, 1, 0, 1)
8,9 (1, 1, 1, 0)
Select your definition for (W,X, Y, Z) from the table above, and complete the following steps:
1. Provide a truth table for F = f(A,B,C,D). [2 marks]
2. Provide an (un-simplified) sum-of-products (SOP) Boolean expression for F , where each product term
contains exactly four (4) variables. [2 marks]
3. Provide a simplified sum-of-products (SOP) Boolean expression for F containing only three (3) variables
in each product term. Include your working. [2 marks]
4. Provide a simplified Boolean expression for F using only ⊕ (XOR) gates. [2 marks]
5. Using a logic diagram, show how F can be implemented using only an 8-to-1 multiplexer. [2 marks]
6. Using a logic diagram, show how F can be implemented using only a 4-to-1 multiplexer and one XOR
gate. [2 marks]
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Task 2 (Circuit Construction Task, 13 marks)
This task requires you to verify the functionality of a given digital circuit by constructing and testing the circuit
on a breadboard. The circuit to be tested is a signed 4-bit comparator as shown in Figure 1 and explained
below.
The functionality of the circuit is to compare two signed 2’s complement 4-bit inputs, A and B, and output
whether A is numerically greater than, equal to or less than B, with three LED outputs. The circuit inputs
and outputs, as well as their IO Board connections, are as follows:
• 4-bit input A ≡ A3A2A1A0, coming from the IO Board switches S7 : S4, also connected to IO board
LEDs L7 : L4.
• 4-bit input B ≡ B3B2B1B0, coming from the IO Board switches S3 : S0, also connected to IO board
LEDs L3 : L0.
• 1-bit output G, which is high when A > B, connected to the segment “a” of the right seven segment
display (SSD) on the IO Board
• 1-bit output E, which is high when A = B, connected to the segment “g” of the right SSD on the IO
Board
• 1-bit output L, which is high when A < B, connected to the segment “d” of the right SSD on the IO
Board
• The right SSD on the IO board can be accessed by connecting the “cc” pin to ground and connecting to
the appropriate segment a-g.
Figure 1: Inputs and outputs of the 4-bit signed comparator circuit. The 4-bit inputs A and B are also
connected to IO board LEDs L7 : L4 and L3 : L0, respectively.
The given circuit can be implemented using a 4-bit adder to perform the subtraction operation (i.e, by computing
(A − B) as A + (−B) using 2’s complement arithmetic) followed by some combinational logic to calculate the
three outputs. As part of this task you will need to design the output logic with some hints provided below.
You should not use more than 4 logic ICs in total. If you use 5 logic ICs, you will lose 1 mark, as per the
marking criteria mentioned at the end. Some guidance on constructing the circuit is also provided and partial
marks will be awarded for demonstrating partial functionality.
• Before you attempt to build the circuit, it is recommended that you complete a paper design, (optionally)
simulate it in Logisim and draw a circuit schematic diagram.
• You must use the 4-bit adder 74HCT283, configured as a subtractor to compute A−B.
• To compute the output E, you need to detect whether the answer A−B is equal to 0, using the available
logic ICs in your kit.
• To compute the output L, you need to detect when A < B in signed 2’s complement. When there is no
overflow, this implies (A−B) < 0. If there is overflow, this implies (A−B) > 0. Your output logic should
capture both these cases. It turns out that computing L can be achieved with simpler logic than G, hence
it might be better to compute L first and then obtain G. However, other options might be possible.
• Once the output L is computed, output G can be computed based on some further logic. Note that, the
output G should exclude the equality case (i.e., G is high when A > B, not A ≥ B). A simple inversion
of output L might not provide output G directly.
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• It is possible to complete the whole design with only 4 logic ICs. You will need to be strategic about choice
of gates and will require a few design iterations to accomplish this. You may want to consider different
ways to calculate the same value as this may result in fewer overall logic chips. It will be difficult to fit
more than 5 logic ICs with the IO board on the breadboard. You will lose 1 mark if your solution
contains 5 logic ICs.
• As part of the submission, you need to include a circuit schematic diagram, which will be useful when you
build, test and troubleshoot your implementation.
Test Cases
To demonstrate the functionality of the circuit, your video must show the following test cases in the given order
for inputs A and B in 4-bit 2’s complement format.
1. Start with all switches set to LOW, resulting in A = B = 0 [1 mark]
2. Set A = 6, B = 3 to show that A > B [1 mark]
3. Set A = 6, B = −3 to show that A > B (cause overflow) [2 marks]
4. Set A = 6, B = 7 to show that A < B [1 mark]
5. Set A = −5, B = −5 to show that A = B [1 mark]
6. Set A = −5, B = −2 to show that A < B [1 mark]
7. Set A = −5, B = 4 to show that A < B (cause overflow) [2 marks]
8. Set A = −5, B = −7 to show that A > B [1 mark]
(−1) marks if five or more logic ICs are used.
Steps to Design & Build the Circuit
To minimise errors in building and testing the circuit, it is highly recommended that you build the circuit
progressively as detailed below, and test the circuit behaviour at each stage. You are only required to submit
a final video showing the operation of the circuit via the tests as outlined above. However, you may want to
record the output of each incremental step below, so that, if your final circuit doesn’t work, you can submit the
outputs of progressive steps and receive partial marks for any correct intermediate outputs. If your final circuit
is fully working, then there is no need to submit the intermediate recordings. Marks will be awarded based on
demonstrated functionality via the given test cases only.
Before constructing the circuit as per the steps below, you must produce a circuit schematic, which needs to
be submitted. You can incrementally construct a logic diagram by following the steps below, which you can
turn into a circuit schematic, making it significantly easier and less error prone to construct. Also, before
constructing the circuit, you may wish to validate your design by testing it on Logisim.
1. Start by implementing the subtraction operation A − B as A + (−B) using the adder IC 74HCT283,
appropriate logic at B input, and LSB carry-in of the adder connected to logic 1. Connect the 4 sum
outputs of the adder to IO Board LEDs L7 : L4 so that the correct operation can be verified. Once
the subtraction circuit is constructed, perform a few test calculations and (optionally) record a video
demonstrating the correct subtraction functionality. For this intermediate step, you may not need to
connect the 8 input bits to 8 LEDs, and just have the output bits connected to 4 LEDs to check the
subtraction output.
2. Compute an overflow detection output (call this V which can be shown on an LED) based on the available
information from A,B, S,C4, where S is the 4-bit sum and C4 is the carry-out from the MSB of the
result. You can optionally record another video demonstrating the correctness of the overflow detection
by demonstrating your test cases.
3. Compute the equal output E, with appropriate combinational logic. You may wish to be strategic in which
logic gates you use to calculate E in order to minimise the total number of logic chips used. Optionally,
record a video showing the correct operation of output E when A = B.
4. Compute the L and G outputs with appropriate logic.
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5. Verify the operation with the suggested test cases. Connect the inputs A and B to LEDs before recording
your circuit demonstrating the test cases.
Submission Process
Your submission should include a zipped folder (a .zip file only, not any other format such as .rar or .7z)
containing your response as follows.
Please submit a zip file containing:
• A .pdf file containing your solution for task 1, your name and 8-digit student number. This can be either
electronically typeset or handwritten and scanned.
• A circuit schematic for your design. Your task 2 will not be marked without a schematic diagram
(either logic diagrams or Logisim screenshots will not be accepted as schematic diagrams).
If you do not submit a schematic diagram which corresponds to the circuit you have built
and tested, you will receive 0 marks for task 2.
• A photo (in .png or .jpg/.jpeg formats) of the constructed circuit. The photo should have your
student ID card visible and should also show the IC numbers that you have used to construct
the circuit (i.e. can be once zoomed-in). The circuit shown in the photo must match with the circuit
shown on the schematic and that in the video. Therefore, take a photo of the circuit, just before you
record the video. If you need to submit a couple of photos to show the IC numbers clearly, that is fine.
• A video (not more than 5 minutes long) showing the required functionality of your circuit, demonstrating
the 8 test cases given above. Prior to demonstrating the test cases using switches, LEDs and SSD, your
video should contain a close-up view of the logic ICs used on your circuit. Successful demonstration of
the 8 test cases will be marked subject to the correctness of the circuit schematic you have submitted.
This single zip file you submit must be named as A1 xxxxxxxx.zip, where xxxxxxxx is your 8-digit student
number, and should be submitted electronically to Blackboard according to the exact instructions listed on the
Blackboard website.
You can submit your assignment multiple times before the deadline but only the last submission before the
deadline will be marked. Only submit the zip file as described above. You are responsible for ensuring that you
have submitted the files that you intended to submit, you are encouraged to download your submission from
Blackboard and ensure it contains the correct files.
Submitted work should be neat, legible and simple to understand - you may be penalised for work that is untidy
or difficult to read.
While you can collaborate to clarify any doubts in the learning material required for the assignment, the work
you submit must be your own and this are an individual assignment. If any signs of plagiarism/collusion
is detected or there are any doubts about the origin of your submission you may be requested to attend a
subsequent oral assessment as decided by the course coordinator. Failure to attend such an oral assessment or
failure to satisfactorily answer questions about your submission will result in zero marks for the assignment.
Late Penalties: Where an assessment item is submitted after the deadline, without an approved extension, a
late penalty will apply. Assessment submissions received after the due time (or any approved extended deadline)
will be subject to a 100% late penalty. A one-hour grace period will be applied to the due time after which
time the 100% late penalty will be imposed.
Criteria
This assignment will be marked out of 25 and is worth 20% of your overall grade.
Task 1 - 12 marks
Truth Table - 2 marks
2: Fully correct truth table.
1: Somewhat correct truth table with less that 4 entries in error.
4
0: Incorrect truth table with more than 4 entries in error or no truth table.
Sum-of-product Boolean Expression - 2 marks
Marked relative to the given truth table, unless there are major omissions.
2: Fully correct expression.
1: Mostly correct expression, with 1-3 terms in error.
0: No logic expression or incorrect logic expression.
Simplified Sum-of-product Boolean Expression - 2 marks
Simplification of SOP expression from previous step. Must contain only three variables in each product term.
2: Fully correct expression with working shown
1: Mostly correct expression with 1-2 terms in error, or does not contain exactly 3 variables in each term
0: No logic expression, incorrect logic expression or not in SOP form.
XOR Boolean Expression - 2 marks
Derived from the simplified SOP Boolean expressions.
2: Fully correct expression involving only XOR gates.
1: Mostly correct expression using only XOR gates with one error.
0: No logic expression or incorrect logic expression.
Logic Diagram with 8-to-1 Multiplexer - 2 marks
Derived from the truth table (unless there are major omissions). Must contain only one 8-to-1 multiplexer.
2: Fully correct logic diagram.
1: Mostly correct logic diagram, with one error or omission.
0: Missing logic diagram or a diagram containing major errors.
Logic Diagram with 4-to-1 Multiplexer and XOR gate - 2 marks
Derived from the truth table (unless there are major omissions). Must contain only one 4-to-1 multiplexer and
one XOR gate
2: Fully correct logic diagram.
1: Mostly correct logic diagram, with one error or omission.
0: Missing logic diagram or a diagram containing major errors.
Task 2 - 13 marks
Marks are awarded based on the demonstrated functionality evident from the video submission subject to cor-
rectness of the circuit schematic. No marks will be awarded for attempting the circuit construction/simulation.
The submission must contain a circuit schematic which corresponds to the circuit shown in the photo and in
the video. If the adder IC 74HCT283 is not used in your design or your submission does not contain a circuit
schematic you will receive 0 marks for the entire task.
Circuit Schematic Diagram - 3 marks
3: Fully correct schematic diagram
2: Mostly correct schematic diagram with minor omissions
1: Somewhat correct schematic diagram with major omissions
0: Incorrect or no schematic diagram
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Demonstrated test cases - marks as indicated above - 10 marks
Partial marks for intermediate steps if the given test cases are not demonstrated
4: Correct subtraction operation with correct overflow detection
2: Correct subtraction with incorrect or no overflow detection
0: Incorrect or no intermediate steps