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Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 1 of 23
This exam paper must not be removed from the venue
School of Information Technology and Electrical Engineering
EXAMINATION
Semester One Final Examinations, 2019
CSSE2010 / CSSE7201 Introduction to Computer Systems
This paper is for St Lucia Campus students.
Examination Duration: 120 minutes
Reading Time: 10 minutes
Exam Conditions:
This is a Central Examination
This is an Open Book Examination
During reading time - write only on the rough paper provided
This examination paper will be released to the Library
Materials Permitted In The Exam Venue:
(No electronic aids are permitted e.g. laptops, phones)
Calculators - Casio FX82 series or UQ approved (labelled)
Materials To Be Supplied To Students:
None
Instructions To Students:
Additional exam materials (eg. answer booklets, rough paper) will be
provided upon request.
All questions should be answered in this exam paper. There are 100 marks total.
Venue ____________________
Seat Number ________
Student Number |__|__|__|__|__|__|__|__|
Family Name _____________________
First Name _____________________
For Examiner Use Only
Question Mark
1
2
3
4
5
6
7
8
9
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 2 of 23
Question 1. (12 marks)
(a) Consider the octal number 1234.
i) Write down the decimal value of this number (1 mark)
ii) Write down the hexadecimal representation of this number (1 mark)
(b) Consider the decimal number –101. Write down the representation of this number in each
of the following binary representations. (1 mark each)
i) 8-bit two’s complement
ii) 8-bit signed magnitude
iii) 9-bit ones’ complement
iv) 8-bit excess-127
2
4
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 3 of 23
Question 1. (continued)
(c) Write down (in hexadecimal) both the IEEE single-precision and double-precision
floating-point representations of –37.375. Show your working. (4 marks)
(d) Consider the 8-bit two’s complement binary numbers 11100111 and 01111001.
i) What is the result (in 8-bit binary) of adding these two numbers? (1 mark)
ii) What would be the values (0 or 1) of the V (overflow), C (carry), N(negative)
and Z (zero) flags after the addition operation in (i) above? (1 mark)
V: C: N: Z:
4
2
Q1
/12
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 4 of 23
Question 2. (12 marks)
(a) Consider the logic function = # + (⨁)+. (. )--------
i) Draw a logic circuit which implements this function. (2 marks)
ii) Complete the following truth table for A. (2 marks)
X Y Z A
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
iii) Write down a sum-of-products expression for A. (2 marks)
A =
2
2
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 5 of 23
Question 2. (continued)
(b) Consider the logic function = + + . 2 .
i) Draw a circuit which implements Z from inputs A, B, C and D using only NAND
gates. (2 marks)
ii) Draw a circuit schematic which implements Z using only the IO Board and chips
from the 74 series logic chips used in the learning labs in this course. The inputs
(A,B,C,D) should come from IO Board push-buttons and the output (Z ) should be
shown on an IO Board LED. (4 marks)
4
2
Q2
/12
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 6 of 23
Question 3. (10 marks)
(a) Draw the logic diagram for a 3-bit synchronous counter which counts in reverse binary
number sequence (i.e. output values 7,6,5,4,3,2,1,0,7,6, …)
Show all your working. (5 marks)
5
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 7 of 23
Question 3. (continued)
(b) A stop-watch like timer has the following functionality. There are two buttons:
R – which when held down (R=1) indicates that the timer should be running, otherwise the
timer should be stopped
C – which when held down (C=1) indicates that the timer should be cleared (i.e. reset to 0).
Note that the C input overrides the R input, i.e. if both are held down, the timer will be
cleared. The timer is implemented as follows:
Draw a state diagram which implements the controller for this timer. There are two inputs
to the controller – R and C as described above. There are two outputs from the controller:
- E (timer enable) – which is 1 when the counter should be counting and 0 otherwise
- Z (timer zero) – which is 1 when the counter should be reset (to 0) and 0 otherwise
(5 marks)
5
Q3
/10
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 8 of 23
Question 4. (14 marks)
Consider the ALU bit slice shown below. [Note that for the output multiplexer on the right
hand side, F2 is the most significant of the select bits, so for example, if F2,F1,F0 =0,0,1 then
input 1 of the multiplexer will be selected.]
(a) Consider 8 of these ALU bit slices put together to form an 8-bit ALU (i.e. with 8-bit data
inputs A and B). Complete the following table to show the required control inputs for the
ALU to perform the given functions. (Each control input will have value 0 or 1 or X
(don’t care). The “carry in” control input applies only to the least significant bit, the
“carry in” input of other bit slices comes from the “carry out” output of its neighbouring
bit slice. The “right shift in” control input applies only to the most significant bit; the
“right shift in” input of other bit slices comes from the “right shift out” output of its
neighbouring bit slice.) If it is not possible to generate the given function, make a
comment to this effect below the table. If there is more than one way to generate the
given function, just show one way.
(1.5 marks each)
Description of
Function Output ENA INVA ENB INVB
Carry
In
Right
Shift
In F2 F1 F0
(i) ⨁ 2 (bitwise)
(ii) A multiplied by 2
(iii) A divided by 2 (if A is
considered to be unsigned)
(iv) 2 . (bitwise)
Ϭ
ϭ
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
KƵƚƉƵƚ
ZŝŐŚƚ^ŚŝĨƚKƵƚ ĂƌƌLJ/Ŷ
/Es
E
E
ZŝŐŚƚ^ŚŝĨƚ/Ŷ ĂƌƌLJKƵƚ
&Ϯ
&ϭ
&Ϭ
/Es
6
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 9 of 23
Question 4. (continued)
(b) Consider a 16-bit binary number stored in AVR registers r4:r5. (r4 holds the most
significant byte, r5 holds the least significant.) Write down a sequence of AVR assembly
language instructions that perform each of the following operations. The result should end
up in r4:r5. Other registers can be used freely if required.
i) Addition of the constant value 9 (decimal) to r4:r5. (2 marks)
ii) Multiplication of r4:r5 by 3 (3 marks)
iii) Division of r4:r5 by 256 if the value in r4:r5 is considered to be unsigned – with the
remainder ending up in r6. (3 marks)
3
Q4
/14
3
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 10 of 23
Question 5. (10 marks)
This question applies to the AVR ATmega324A microcontroller. What will be the binary
value in register r30 after the execution of the nominated instructions (i) to (x) in the
sequence of instructions below. Note that the instructions are not independent – registers and
RAM maintain their values from one instruction to the next. You may assume that the stack
pointer has been appropriately initialised. (1 mark each)
clr r30
push r30
i) ldi r30, -1 r30:
push r30
ii) neg r30 r30:
iii) ldi r30, 032 r30:
iv) ldi r30, 0x9B r30:
push r30
v) com r30 r30:
ldi r30, 0xBE
vi) andi r30, 0xEC r30:
ldi r30, 0xBE
vii) asr r30 r30:
ldi r30, 0xBE
ldi ZH, 2
viii) sbiw ZH:ZL, 33 r30:
ix) pop r30 r30:
ldi r30, 0xBE
x) ld r29,Z+ r30:
Q5
/10
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 11 of 23
Question 6. (12 marks)
For each of the following C statements for the Atmel AVR ATmega324A, write down the
assembly language equivalent. (You may assume that definitions in the m324Adef.inc file are
available. Several instructions may be required.)
(a) OCR0A = 0; (1 mark)
(b) EEDR = PINA; (1 mark)
(c) OCR1B = 1692; (2 marks)
(d) TIMSK0 |= (1<
2
1
2
1
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 12 of 23
Question 6. (continued)
(e) TCNT1 += 300; (2 marks)
(f) ADMUX |= (1<DDRB = 0xFF;
PORTB = (ADC >> 8); (2 marks)
(g) while (!(TWCR &(1< ;
} (2 marks)
2
2
Q6
/12
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 13 of 23
Question 7. (12 marks)
The following is an edited extracted from Section 23.9 of the AVR ATmega324A datasheet.
You will need to refer to this information when answering this question.
23.9 Analog to Digital Converter – Register Description
23.9.1 ADMUX – ADC Multiplexer Selection Register
Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 23-3. If these bits are changed
during a conversion, the change will not go into effect until this conversion is complete (ADIF in
ADCSRA is set). The internal voltage reference options may not be used if an external reference
voltage is being applied to the AREF pin.
Table 23-3. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selection for ADC
0 0 AREF, Internal Vref turned off.
0 1 AVCC with external capacitor at AREF pin
1 0 Internal 1.1V Voltage Reference with external capacitor at AREF pin
1 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write
one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit
will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete
description of this bit, see “23.9.3 ADCL and ADCH – The ADC Data Register” below.
Bits 4:0 – MUX4:0: Analog Channel Selection Bits
The value of these bits selects which analog input is connected to the ADC. See Table 23-4 for
details. If these bits are changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSRA is set).
Table 23-4. Input Channel Selection
MUX4..0 Input
00000 ADC0
00001 ADC1
00010 ADC2
00011 ADC3
00100 ADC4
00101 ADC5
00110 ADC6
00111 ADC7
11111 0V (GND)
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 14 of 23
23.9.2 ADCSRA – ADC Control and Status Register A
Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC
off while a conversion is in progress, will terminate this conversion.
Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running Mode, write
this bit to one to start the first conversion. The first conversion after ADSC has been written after the
ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25
ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it
returns to zero. Writing zero to this bit has no effect.
Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled, i.e. free running mode – the
next conversion will start immediately after the previous conversion.
Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC
Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF
is cleared by writing a logical one to the flag.
Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is
activated.
Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the
ADC. The default value (000) will result in division by 2 – the fastest rate.
23.9.3 ADCL and ADCH – The ADC Data Register
ADLAR=0 (Right Adjusted)
ADLAR=1 (Left Adjusted)
When an ADC conversion is complete, the result is found in these two registers. When ADCL is read,
the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL
must be read first, then ADCH. The ADLAR bit in ADMUX affects the way the result is read from the
registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right
adjusted.
ADC9:0: ADC Conversion Result
These bits represent the result from the conversion.
23.9.4. ADCSRB – ADC Control and Status Register B
If ADATE in ADCSRA is written to one, the default value of this register will result in the ADC operating
in free running mode (i.e. a new conversion starts as soon as the previous one finishes).
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 15 of 23
Question 7. (continued)
(a) Write a C function
uint8_t configure_adc(uint8_t adcinput)
for the AVR ATmega324A microcontroller. The function configures the ADC to perform
conversions on the given ADC input in free-running mode, starting immediately, with a
voltage reference of AVCC. Interrupts must be enabled for when conversions complete.
The single argument (adcinput) should be a number from 0 to 7 inclusive. The
function must return 1 and do nothing if the adcinput argument is out of range,
otherwise, it must configure the ADC appropriately and return 0. State any assumptions
you need to make as comments in the code. (6 marks)
uint8_t configure_adc(uint8_t adcinput)
{
}
6
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 16 of 23
Question 7. (continued)
(b) Assuming that the analog to digital converter is configured as described in Question 7(a),
write an AVR assembly language interrupt handler for the ATmega324A that will be
called when an ADC conversion completes. The handler must output the 4 most
significant bits of the conversion value to the four least significant bits of the port B pins
with 0 being output to the four most significant bits of the port B pins. (You can assume
that the port B pins have been previously configured as outputs.) The interrupt handler
must preserve the values of all general-purpose registers and the status register (i.e. these
register values must be restored to their original values if they are changed by the
handler). (6 marks)
6
Q7
/12
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 17 of 23
Question 8. (8 marks)
Consider the following AVR ATmega324A assembly language module and answer the
questions on the following page.
.include “m324Adef.inc”
.equ INPUT_BUFFER_SIZE = 16
.equ NEWLINE = 10
.cseg
charconstants: .DB NEWLINE
.dseg
input_buffer: .BYTE INPUT_BUFFER_SIZE
bytes_in_input_buffer: .BYTE 1
input_insert_pos: .BYTE 1
.cseg
uart_get_char:
lds r24, bytes_in_input_buffer
tst r24
breq uart_get_char
save_interrupt_status:
in r18, SREG
andi r18, 0x80
cli
lds r24, input_insert_pos
lds r19, bytes_in_input_buffer
ldi r25, 0
sub r24, r19
sbc r25, r1
brpl extract_char
extract_char_and_wrap_buffer:
lds ZL, input_insert_pos
lds r24, bytes_in_input_buffer
ldi ZH, 0
sub ZL, r24
sbc r31, r1
subi ZL, 255-low(input_buffer-INPUT_BUFFER_SIZE)
sbci ZH, 255-high(input_buffer-INPUT_BUFFER_SIZE)
ld r24, Z
rjmp decrement_buffer_count
extract_char:
lds ZL, input_insert_pos
lds r24, bytes_in_input_buffer
ldi ZH, 0
sub ZL, r24
sbc ZH, r1
subi ZL, 255-low(input_buffer)
sbci ZH, 255-high(input_buffer)
ld r24, Z
decrement_buffer_count:
lds r24, bytes_in_input_buffer
subi r25, 1
sts bytes_in_input_buffer, r25
tst r18
breq done
sei
done:
ldi r25, 0
ret
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 18 of 23
Question 8. (continued)
(a) What is the overall size (in instruction words) of the code segment for this module? (1 mark)
(b) What is the overall size (in bytes) of the data segment for this module? (1 mark)
(c) The module shown above (which we will now call module C) is linked with three other
modules (A, B and D) with code and data segment sizes as shown:
Module Code segment size
(instruction words)
Data segment size
(bytes)
A 56 32
B 75 48
D 91 17
If the modules are linked in order A, B, C and D starting from code segment address 0x3E
(62 decimal) and data segment address 0x100 (256 decimal), determine the code and data
segment relocation constants (in decimal) for all modules. (4 marks)
Module A Module B Module C Module D
Code Segment Relocation Constant
Data Segment Relocation Constant
(d) After linking as described in (c), at what memory address (in decimal) will the variable
bytes_in_input_buffer be found? (1 mark)
(e) After linking as described in (c), at what instruction word address (in decimal) will the
instruction at label save_interrupt_status be found? (1 mark)
1
1
1
1
Q8
/8
4
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 19 of 23
Question 9. (10 marks)
(a) The Western Digital Ultrastar HUS728T8TALN6L4 hard drive has the following
specifications:
Nominal Capacity: 8TB (1TB = 1012 bytes)
Sector size: 4096 bytes
Rotational speed: 7200 RPM
Max Sustained transfer rate: 255MB/s (1MB = 106 bytes)
Average seek time (typical): 8.0ms (read) / 8.6ms (write)
The hard drive is formatted with a file system that has a block size of 32kB (32,768 bytes)
and currently contains 1,000,000 files of various sizes which occupy 50,000,000 data
blocks.
i) What is the average access time when writing to the disk? (Show your working.)
(2 marks)
ii) How much total space within the 50,000,000 allocated data blocks is likely to be
wasted (i.e. not used for storing data)? (Show your working. Express your answer in
kB, where 1kB=1024 bytes). (2 marks)
iii) If the file system overhead is 5% of the total disk capacity, how many additional files
each of size 200kB (200 x 1024 bytes) could be saved on the disk? (Show your
working.)
(2 marks)
2
2
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 20 of 23
Question 9. (continued)
iv) The hard disk is connected to a computer via a USB 3.0 interface. Approximately
how long will it take to copy all 1,000,000 files from the disk? (Show your working.
State all assumptions.)
(2 marks)
(b) Consider a big-endian computer with a memory which has an addressable cell size of one
byte and which requires natural alignment. The values in memory cells 272 to 280
inclusive are as shown in the table below.
i) If the system has a data bus width of 16 bits, how many memory reads will be
required to read the 32-bit unsigned integer stored at address 300? (1 mark)
ii) If the computer stores the 32-bit unsigned value 0x72012010 to address 276, show
the contents (in hexadecimal) of the memory cells which are changed by this
operation.
(1 mark)
Initial Value (hexadecimal) New Value (if changed)
272: F1
273: 2E
274: D3
275: 4C
276: B5
277: 6A
278: 97
279: 88
280: 79
END OF EXAMINATION PAPER
2
2
Q9
/10
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 21 of 23
This page is provided for rough or additional working and will not be marked unless an earlier
answer explicitly refers to a continuation of an answer on this page.
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 22 of 23
This page is provided for rough or additional working and will not be marked unless an earlier
answer explicitly refers to a continuation of an answer on this page.
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 23 of 23
This page is provided for rough or additional working and will not be marked unless an earlier
answer explicitly refers to a continuation of an answer on this page.
Page 1 of 23
This exam paper must not be removed from the venue
School of Information Technology and Electrical Engineering
EXAMINATION
Semester One Final Examinations, 2019
CSSE2010 / CSSE7201 Introduction to Computer Systems
This paper is for St Lucia Campus students.
Examination Duration: 120 minutes
Reading Time: 10 minutes
Exam Conditions:
This is a Central Examination
This is an Open Book Examination
During reading time - write only on the rough paper provided
This examination paper will be released to the Library
Materials Permitted In The Exam Venue:
(No electronic aids are permitted e.g. laptops, phones)
Calculators - Casio FX82 series or UQ approved (labelled)
Materials To Be Supplied To Students:
None
Instructions To Students:
Additional exam materials (eg. answer booklets, rough paper) will be
provided upon request.
All questions should be answered in this exam paper. There are 100 marks total.
Venue ____________________
Seat Number ________
Student Number |__|__|__|__|__|__|__|__|
Family Name _____________________
First Name _____________________
For Examiner Use Only
Question Mark
1
2
3
4
5
6
7
8
9
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 2 of 23
Question 1. (12 marks)
(a) Consider the octal number 1234.
i) Write down the decimal value of this number (1 mark)
ii) Write down the hexadecimal representation of this number (1 mark)
(b) Consider the decimal number –101. Write down the representation of this number in each
of the following binary representations. (1 mark each)
i) 8-bit two’s complement
ii) 8-bit signed magnitude
iii) 9-bit ones’ complement
iv) 8-bit excess-127
2
4
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 3 of 23
Question 1. (continued)
(c) Write down (in hexadecimal) both the IEEE single-precision and double-precision
floating-point representations of –37.375. Show your working. (4 marks)
(d) Consider the 8-bit two’s complement binary numbers 11100111 and 01111001.
i) What is the result (in 8-bit binary) of adding these two numbers? (1 mark)
ii) What would be the values (0 or 1) of the V (overflow), C (carry), N(negative)
and Z (zero) flags after the addition operation in (i) above? (1 mark)
V: C: N: Z:
4
2
Q1
/12
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 4 of 23
Question 2. (12 marks)
(a) Consider the logic function = # + (⨁)+. (. )--------
i) Draw a logic circuit which implements this function. (2 marks)
ii) Complete the following truth table for A. (2 marks)
X Y Z A
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
iii) Write down a sum-of-products expression for A. (2 marks)
A =
2
2
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 5 of 23
Question 2. (continued)
(b) Consider the logic function = + + . 2 .
i) Draw a circuit which implements Z from inputs A, B, C and D using only NAND
gates. (2 marks)
ii) Draw a circuit schematic which implements Z using only the IO Board and chips
from the 74 series logic chips used in the learning labs in this course. The inputs
(A,B,C,D) should come from IO Board push-buttons and the output (Z ) should be
shown on an IO Board LED. (4 marks)
4
2
Q2
/12
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 6 of 23
Question 3. (10 marks)
(a) Draw the logic diagram for a 3-bit synchronous counter which counts in reverse binary
number sequence (i.e. output values 7,6,5,4,3,2,1,0,7,6, …)
Show all your working. (5 marks)
5
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 7 of 23
Question 3. (continued)
(b) A stop-watch like timer has the following functionality. There are two buttons:
R – which when held down (R=1) indicates that the timer should be running, otherwise the
timer should be stopped
C – which when held down (C=1) indicates that the timer should be cleared (i.e. reset to 0).
Note that the C input overrides the R input, i.e. if both are held down, the timer will be
cleared. The timer is implemented as follows:
Draw a state diagram which implements the controller for this timer. There are two inputs
to the controller – R and C as described above. There are two outputs from the controller:
- E (timer enable) – which is 1 when the counter should be counting and 0 otherwise
- Z (timer zero) – which is 1 when the counter should be reset (to 0) and 0 otherwise
(5 marks)
5
Q3
/10
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 8 of 23
Question 4. (14 marks)
Consider the ALU bit slice shown below. [Note that for the output multiplexer on the right
hand side, F2 is the most significant of the select bits, so for example, if F2,F1,F0 =0,0,1 then
input 1 of the multiplexer will be selected.]
(a) Consider 8 of these ALU bit slices put together to form an 8-bit ALU (i.e. with 8-bit data
inputs A and B). Complete the following table to show the required control inputs for the
ALU to perform the given functions. (Each control input will have value 0 or 1 or X
(don’t care). The “carry in” control input applies only to the least significant bit, the
“carry in” input of other bit slices comes from the “carry out” output of its neighbouring
bit slice. The “right shift in” control input applies only to the most significant bit; the
“right shift in” input of other bit slices comes from the “right shift out” output of its
neighbouring bit slice.) If it is not possible to generate the given function, make a
comment to this effect below the table. If there is more than one way to generate the
given function, just show one way.
(1.5 marks each)
Description of
Function Output ENA INVA ENB INVB
Carry
In
Right
Shift
In F2 F1 F0
(i) ⨁ 2 (bitwise)
(ii) A multiplied by 2
(iii) A divided by 2 (if A is
considered to be unsigned)
(iv) 2 . (bitwise)
Ϭ
ϭ
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
KƵƚƉƵƚ
ZŝŐŚƚ^ŚŝĨƚKƵƚ ĂƌƌLJ/Ŷ
/Es
E
E
ZŝŐŚƚ^ŚŝĨƚ/Ŷ ĂƌƌLJKƵƚ
&Ϯ
&ϭ
&Ϭ
/Es
6
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 9 of 23
Question 4. (continued)
(b) Consider a 16-bit binary number stored in AVR registers r4:r5. (r4 holds the most
significant byte, r5 holds the least significant.) Write down a sequence of AVR assembly
language instructions that perform each of the following operations. The result should end
up in r4:r5. Other registers can be used freely if required.
i) Addition of the constant value 9 (decimal) to r4:r5. (2 marks)
ii) Multiplication of r4:r5 by 3 (3 marks)
iii) Division of r4:r5 by 256 if the value in r4:r5 is considered to be unsigned – with the
remainder ending up in r6. (3 marks)
3
Q4
/14
3
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 10 of 23
Question 5. (10 marks)
This question applies to the AVR ATmega324A microcontroller. What will be the binary
value in register r30 after the execution of the nominated instructions (i) to (x) in the
sequence of instructions below. Note that the instructions are not independent – registers and
RAM maintain their values from one instruction to the next. You may assume that the stack
pointer has been appropriately initialised. (1 mark each)
clr r30
push r30
i) ldi r30, -1 r30:
push r30
ii) neg r30 r30:
iii) ldi r30, 032 r30:
iv) ldi r30, 0x9B r30:
push r30
v) com r30 r30:
ldi r30, 0xBE
vi) andi r30, 0xEC r30:
ldi r30, 0xBE
vii) asr r30 r30:
ldi r30, 0xBE
ldi ZH, 2
viii) sbiw ZH:ZL, 33 r30:
ix) pop r30 r30:
ldi r30, 0xBE
x) ld r29,Z+ r30:
Q5
/10
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 11 of 23
Question 6. (12 marks)
For each of the following C statements for the Atmel AVR ATmega324A, write down the
assembly language equivalent. (You may assume that definitions in the m324Adef.inc file are
available. Several instructions may be required.)
(a) OCR0A = 0; (1 mark)
(b) EEDR = PINA; (1 mark)
(c) OCR1B = 1692; (2 marks)
(d) TIMSK0 |= (1<
2
1
2
1
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 12 of 23
Question 6. (continued)
(e) TCNT1 += 300; (2 marks)
(f) ADMUX |= (1<
PORTB = (ADC >> 8); (2 marks)
(g) while (!(TWCR &(1<
} (2 marks)
2
2
Q6
/12
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 13 of 23
Question 7. (12 marks)
The following is an edited extracted from Section 23.9 of the AVR ATmega324A datasheet.
You will need to refer to this information when answering this question.
23.9 Analog to Digital Converter – Register Description
23.9.1 ADMUX – ADC Multiplexer Selection Register
Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 23-3. If these bits are changed
during a conversion, the change will not go into effect until this conversion is complete (ADIF in
ADCSRA is set). The internal voltage reference options may not be used if an external reference
voltage is being applied to the AREF pin.
Table 23-3. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selection for ADC
0 0 AREF, Internal Vref turned off.
0 1 AVCC with external capacitor at AREF pin
1 0 Internal 1.1V Voltage Reference with external capacitor at AREF pin
1 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write
one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit
will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete
description of this bit, see “23.9.3 ADCL and ADCH – The ADC Data Register” below.
Bits 4:0 – MUX4:0: Analog Channel Selection Bits
The value of these bits selects which analog input is connected to the ADC. See Table 23-4 for
details. If these bits are changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSRA is set).
Table 23-4. Input Channel Selection
MUX4..0 Input
00000 ADC0
00001 ADC1
00010 ADC2
00011 ADC3
00100 ADC4
00101 ADC5
00110 ADC6
00111 ADC7
11111 0V (GND)
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 14 of 23
23.9.2 ADCSRA – ADC Control and Status Register A
Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC
off while a conversion is in progress, will terminate this conversion.
Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running Mode, write
this bit to one to start the first conversion. The first conversion after ADSC has been written after the
ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25
ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it
returns to zero. Writing zero to this bit has no effect.
Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled, i.e. free running mode – the
next conversion will start immediately after the previous conversion.
Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC
Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF
is cleared by writing a logical one to the flag.
Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is
activated.
Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the
ADC. The default value (000) will result in division by 2 – the fastest rate.
23.9.3 ADCL and ADCH – The ADC Data Register
ADLAR=0 (Right Adjusted)
ADLAR=1 (Left Adjusted)
When an ADC conversion is complete, the result is found in these two registers. When ADCL is read,
the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL
must be read first, then ADCH. The ADLAR bit in ADMUX affects the way the result is read from the
registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right
adjusted.
ADC9:0: ADC Conversion Result
These bits represent the result from the conversion.
23.9.4. ADCSRB – ADC Control and Status Register B
If ADATE in ADCSRA is written to one, the default value of this register will result in the ADC operating
in free running mode (i.e. a new conversion starts as soon as the previous one finishes).
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 15 of 23
Question 7. (continued)
(a) Write a C function
uint8_t configure_adc(uint8_t adcinput)
for the AVR ATmega324A microcontroller. The function configures the ADC to perform
conversions on the given ADC input in free-running mode, starting immediately, with a
voltage reference of AVCC. Interrupts must be enabled for when conversions complete.
The single argument (adcinput) should be a number from 0 to 7 inclusive. The
function must return 1 and do nothing if the adcinput argument is out of range,
otherwise, it must configure the ADC appropriately and return 0. State any assumptions
you need to make as comments in the code. (6 marks)
uint8_t configure_adc(uint8_t adcinput)
{
}
6
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 16 of 23
Question 7. (continued)
(b) Assuming that the analog to digital converter is configured as described in Question 7(a),
write an AVR assembly language interrupt handler for the ATmega324A that will be
called when an ADC conversion completes. The handler must output the 4 most
significant bits of the conversion value to the four least significant bits of the port B pins
with 0 being output to the four most significant bits of the port B pins. (You can assume
that the port B pins have been previously configured as outputs.) The interrupt handler
must preserve the values of all general-purpose registers and the status register (i.e. these
register values must be restored to their original values if they are changed by the
handler). (6 marks)
6
Q7
/12
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 17 of 23
Question 8. (8 marks)
Consider the following AVR ATmega324A assembly language module and answer the
questions on the following page.
.include “m324Adef.inc”
.equ INPUT_BUFFER_SIZE = 16
.equ NEWLINE = 10
.cseg
charconstants: .DB NEWLINE
.dseg
input_buffer: .BYTE INPUT_BUFFER_SIZE
bytes_in_input_buffer: .BYTE 1
input_insert_pos: .BYTE 1
.cseg
uart_get_char:
lds r24, bytes_in_input_buffer
tst r24
breq uart_get_char
save_interrupt_status:
in r18, SREG
andi r18, 0x80
cli
lds r24, input_insert_pos
lds r19, bytes_in_input_buffer
ldi r25, 0
sub r24, r19
sbc r25, r1
brpl extract_char
extract_char_and_wrap_buffer:
lds ZL, input_insert_pos
lds r24, bytes_in_input_buffer
ldi ZH, 0
sub ZL, r24
sbc r31, r1
subi ZL, 255-low(input_buffer-INPUT_BUFFER_SIZE)
sbci ZH, 255-high(input_buffer-INPUT_BUFFER_SIZE)
ld r24, Z
rjmp decrement_buffer_count
extract_char:
lds ZL, input_insert_pos
lds r24, bytes_in_input_buffer
ldi ZH, 0
sub ZL, r24
sbc ZH, r1
subi ZL, 255-low(input_buffer)
sbci ZH, 255-high(input_buffer)
ld r24, Z
decrement_buffer_count:
lds r24, bytes_in_input_buffer
subi r25, 1
sts bytes_in_input_buffer, r25
tst r18
breq done
sei
done:
ldi r25, 0
ret
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 18 of 23
Question 8. (continued)
(a) What is the overall size (in instruction words) of the code segment for this module? (1 mark)
(b) What is the overall size (in bytes) of the data segment for this module? (1 mark)
(c) The module shown above (which we will now call module C) is linked with three other
modules (A, B and D) with code and data segment sizes as shown:
Module Code segment size
(instruction words)
Data segment size
(bytes)
A 56 32
B 75 48
D 91 17
If the modules are linked in order A, B, C and D starting from code segment address 0x3E
(62 decimal) and data segment address 0x100 (256 decimal), determine the code and data
segment relocation constants (in decimal) for all modules. (4 marks)
Module A Module B Module C Module D
Code Segment Relocation Constant
Data Segment Relocation Constant
(d) After linking as described in (c), at what memory address (in decimal) will the variable
bytes_in_input_buffer be found? (1 mark)
(e) After linking as described in (c), at what instruction word address (in decimal) will the
instruction at label save_interrupt_status be found? (1 mark)
1
1
1
1
Q8
/8
4
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 19 of 23
Question 9. (10 marks)
(a) The Western Digital Ultrastar HUS728T8TALN6L4 hard drive has the following
specifications:
Nominal Capacity: 8TB (1TB = 1012 bytes)
Sector size: 4096 bytes
Rotational speed: 7200 RPM
Max Sustained transfer rate: 255MB/s (1MB = 106 bytes)
Average seek time (typical): 8.0ms (read) / 8.6ms (write)
The hard drive is formatted with a file system that has a block size of 32kB (32,768 bytes)
and currently contains 1,000,000 files of various sizes which occupy 50,000,000 data
blocks.
i) What is the average access time when writing to the disk? (Show your working.)
(2 marks)
ii) How much total space within the 50,000,000 allocated data blocks is likely to be
wasted (i.e. not used for storing data)? (Show your working. Express your answer in
kB, where 1kB=1024 bytes). (2 marks)
iii) If the file system overhead is 5% of the total disk capacity, how many additional files
each of size 200kB (200 x 1024 bytes) could be saved on the disk? (Show your
working.)
(2 marks)
2
2
2
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 20 of 23
Question 9. (continued)
iv) The hard disk is connected to a computer via a USB 3.0 interface. Approximately
how long will it take to copy all 1,000,000 files from the disk? (Show your working.
State all assumptions.)
(2 marks)
(b) Consider a big-endian computer with a memory which has an addressable cell size of one
byte and which requires natural alignment. The values in memory cells 272 to 280
inclusive are as shown in the table below.
i) If the system has a data bus width of 16 bits, how many memory reads will be
required to read the 32-bit unsigned integer stored at address 300? (1 mark)
ii) If the computer stores the 32-bit unsigned value 0x72012010 to address 276, show
the contents (in hexadecimal) of the memory cells which are changed by this
operation.
(1 mark)
Initial Value (hexadecimal) New Value (if changed)
272: F1
273: 2E
274: D3
275: 4C
276: B5
277: 6A
278: 97
279: 88
280: 79
END OF EXAMINATION PAPER
2
2
Q9
/10
Semester One Final Examinations, 2019 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 21 of 23
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