Semester Two Final Examinations, 2021 CSSE2010/CSSE7201 Introduction to Computer Systems
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This exam paper must not be removed from the venue
Venue ____________________
Seat Number __________
Student Number |__|__|__|__|__|__|__|__|
Family Name ____________________
First Name ____________________
School of Information Technology and Electrical Engineering
EXAMINATION
Semester Two Final Examinations, 2021
CSSE2010/7201 Introduction to Computer Systems
This paper is for St Lucia Campus students (All internal delivery students and external mode students
who have been approved for an on-campus exam)
Examination Duration: 120 minutes
Reading Time: 10 minutes
Exam Conditions:
This is an Open Book examination
Casio FX82 series or a calculator on the UQ approved list
During reading time (= planning time) - students are encouraged to
review and plan responses to the exam questions
This examination paper will be released to the Library
Materials Permitted In The Exam Venue:
(No electronic aids are permitted e.g. laptops, phones, e-readers)
Calculators - Casio FX82 series or UQ approved (labelled)
Written or printed material is allowed
Materials To Be Supplied To Students:
None
Instructions To Students:
Additional exam materials (e.g. answer booklets, rough paper) will
be provided upon request.
Answer all questions on this exam paper.
Questions are worth the number of marks indicated
For Examiner Use Only
TOTAL:
Question
Mark
1
2
3
4
5
6
7
Semester Two Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
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Question 1. (11 marks)
(a) Fill in the following table to complete different number representations of a given
number. Each row corresponds to one number which is represented across different
formats in each column for that row. There are 9 blanks to be filled. (4.5 marks)
Decimal 6-bit signed binary
1’s complement
6-bit signed binary
2’s complement
6-bit signed binary
excess -32
101011
110110
101101
(b) In a number system with base (i.e. radix) 258 what is the 4-digit representation of the
number 258? (1 mark)
4.5
1
Semester Two Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
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(c) Consider the two 8-bit binary two’s complement signed numbers A=10010101 and
B=11001011.
i) What is the result of A+B in 8-bit binary? (2 marks)
ii) What are the values (0 or 1) of negative (N), zero (Z), carry (C) and overflow (V)
flags after completing the above addition in c-i? (2 marks)
N: Z: C: V:
(d) What is the (decimal) interpretation of the IEEE single-precision floating point number
0x7FB80012? Show your working. (1.5 marks)
4
1.5
Q1
/11
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Question 2. (14 marks)
Consider the following truth table for a 3-input Boolean function F.
A B C F
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
(a) Provide the sum-of-product Boolean expression for function F (2 marks)
(b) Provide a logic diagram for computing function F from inputs A, B, C only using 2-input
AND, OR, NOT gates (2 marks)
(c) Provide a logic diagram for the 2-input NOR equivalent circuit of part (b) for computing
function F (2 marks)
2
2
2
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(d) Using a diagram, show how you can implement the logic function F using a,
i) 4 to 1 multiplexer and NOT gates (4 marks)
ii) 3 to 8 decoder and basic (AND/OR/NOT) gates (4 marks)
4
4
Q2
/14
Semester Two Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
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Question 3. (20 marks)
You are required to design a controller for a vending machine using a finite state machine
(FSM) based on positive edge triggered D flip flops. The vending machine operates as
follows:
• The machine accepts either $1 or $2 coins only but not at the same time (i.e. the user
can insert one coin at a time or not insert any coins).
• When the total money entered is greater than or equal $3, the machine dispenses a soft
drink bottle and also gives change if there is any.
• The machine has 2 external inputs called X and Y and 2 outputs called F and G
• Input X represents $1-coin sensor and input Y represents the $2-coin sensor with the
following valid input combinations
o X=0, Y=0 - no coin is inserted
o X=1, Y=0 - $1 is inserted
o X=0, Y=1 - $2 is inserted
o X=1, Y=1 – invalid input and you can assume that this never happens
• The system is driven by an internally generated clock signal
• The two outputs F and G are for dispense and change, respectively. F=1 implies the
bottle is dispensed upon receiving the correct value of money and F=0 implies not
enough money to dispense the bottle. The output G=1 implies that change is given to
the user and G=0 for no change.
• Once a bottle is dispensed, in the next clock edge, the system goes back to the initial
state with a total of $0.
• The system has an asynchronous reset operation which you do not need to consider in
the design.
• If you make any other assumptions answering the questions below, please state them
explicitly.
(a) Provide a Moore type state diagram for the vending machine controller. Your state
diagram should contain state names, outputs and input transitions marked with variables
X and Y and should be complete. You can ignore the input combination (X=1, Y=1) as
this is assumed to be invalid and never happens. (5 marks)
5
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(b) Provide a 2D state table for the state machine in (a) with an appropriate state encoding.
Hint: you may select an encoding scheme having a smaller number of 1’s in the binary
patterns for each state as this would reduce the complexity of the expressions. You do not
need to consider any unused states in the design, hence no need to consider any don’t care
terms. (8 marks)
(c) Using the 2D state table in (b) obtain Boolean expressions for the flip flop inputs D’s and
the two outputs F and G. You do not need to simplify the expressions, but you may
attempt any straightforward simplifications which may simplify your answer for the next
part (5 marks)
8
5
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(d) Using the expressions in (c), obtain a logic diagram for the FSM using positive edge
triggered D flip flops and other gates as required. You do not need to show the
asynchronous preset/clear inputs of the flip flops, thus, you are not required to show the
asynchronous reset operation in your diagram. You can use gates with any number of
inputs (2 marks)
2
Q3
/20
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Question 4. (8 marks)
Consider the ALU bit slice shown below. [Note that for the output multiplexer on the right
hand side, F2 is the most significant of the select bits, so for example, if F2,F1,F0 =0,0,1 then
input 1 of the multiplexer will be selected.]
Consider 16 of these ALU bit slices put together to form an 16-bit ALU (i.e. with 16-bit data
inputs A and B). Complete the following table to show the required control inputs for the
ALU to perform the given functions. (Each control input will have value 0 or 1 or X (don’t
care). The “carry in” control input applies only to the least significant bit, the “carry in” input
of other bit slices comes from the “carry out” output of its neighbouring bit slice. The “right
shift in” control input applies only to the most significant bit; the “right shift in” input of other
bit slices comes from the “right shift out” output of its neighbouring bit slice.) If it is not
possible to generate the given function, make a comment to this effect below the table. If
there is more than one way to generate the given function, just show one way.
(2 marks each)
Description of
Function Output ENA INVA ENB INVB
Carry
In
Right
Shift
In F2 F1 F0
(i) Constant value (-1)
(ii) Increment B (i.e., B+1)
(iii) Logical shift left of B
(iv) # . & (bitwise)(. is AND)
Ϭ
ϭ
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
KƵƚƉƵƚ
ZŝŐŚƚ^ŚŝĨƚKƵƚ ĂƌƌLJ/Ŷ
/Es
E
E
ZŝŐŚƚ^ŚŝĨƚ/Ŷ ĂƌƌLJKƵƚ
&Ϯ
&ϭ
&Ϭ
/Es
Q4
/8
Semester Two Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
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Question 5. (16 marks)
This question applies to the AVR ATmega324A microcontroller and associated assembly
language instructions.
(a) Write down the machine code corresponding to the AVR assembly language instruction
cp r5, r14 (1 mark)
(b) Consider four 16-bit signed 2’s complement values A, B, C, and D stored in pairs of
general purpose registers [r5:r6], [r7:r8], [r9:r10], [r11:r12], respectively. That is, A is
stored in register pair [r5:r6] with the most significant byte in r5 and the least significant
byte in r6, and so on. Write an assembly language code segment to compute the average
of the four values given by (A+B+C+D)/4 and the result should be stored in the register
pair [r11:r12] with the most significant byte in r11 and the least significant byte in r12.
Other general-purpose registers can be used freely. (4 marks)
(c) Write an assembly language code segment to initialise a 24-bit signed variable (in two’s
complement) stored in registers r8:r9:410 to value (-4). r8 contains the most significant
byte and r10 contains the least significant byte. (2 marks)
1
4
2
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(d) Consider the assembly language code segment given below
.def index=r16
.def maxindex=r17
.def sum=r20
ldi maxindex,20
clr index
clr sum
loop: cp index, maxindex
bge exit
add sum, index
inc index
jmp loop
exit: nop
(i) Provide a verbal explanation on what the above code is doing including the values
of the registers r16 and r20 after execution of the above code. (3 mark)
(ii) How many bytes in program memory does the above code occupy? (2 marks)
(iii) How many clock cycles does the above code take to execute? (2 marks)
(iv) If the instruction jmp is replaced by rjmp how many clock cycles can be saved?
(2 marks)
3
2
2
2
Q5
/16
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Question 6. (17 marks)
(a) For each of the following C statements for the Atmel AVR ATmega324A, write down the
assembly language equivalent. (You may assume that definitions in the m324Adef.inc file
are available. Several instructions may be required. You can freely use general purpose
registers).
(i) PORTD = PINA; (2 marks)
(ii) EECR |= (1<
(iii) UBRR0 = UBRR1; (3 marks)
2
2
3
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The following is an edited extracted from Section 19.11 of the ATmega324A datasheet. You
will need to refer to this information when answering this question.
19.11.1. TC2 Control Register A
Name: TCCR2A
Offset: 0xB0
Bits 7:6 – COM2An: Compare Output Mode for Channel A [n = 1:0]
The table below shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast
PWM
mode.
Table 19-4. Compare Output Mode, Fast PWM
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected WGM22 = 1: Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match, set OC2A at BOTTOM, (non-inverting mode)
1 1 Set OC2A on Compare Match, clear OC2A at BOTTOM, (inverting-mode)
Note: A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case the
compare
match is ignored, but the set or clear is done at BOTTOM.
Bits 5:4 – COM2Bn: Compare Output Mode for Channel B [n = 1:0]
The table below shows the COM2B[1:0] bit functionality when the WGM0[2:0] bits are set to fast
PWM
mode.
Table 19-7. Compare Output Mode, Fast PWM
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Reserved
1 0 Clear OC2B on Compare Match, set OC2B at BOTTOM, (non-inverting mode)
1 1 Set OC2B on Compare Match, clear OC2B at BOTTOM, (inverting-mode)
Note: A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the
Compare Match is ignored, but the set or clear is done at TOP.
Bits 1:0 – WGM2n: Waveform Generation Mode [n = 1:0]
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation is to be used. Modes of operation supported by the Timer/Counter unit are: Normal
mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width
Modulation (PWM) modes.
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Table 19-9. Waveform Generation Mode Bit Description
Note:
1. MAX = 0xFF
2. BOTTOM = 0x00
19.11.2. TC2 Control Register B
Name: TCCR2B
Offset: 0xB1
Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
Bit 3 – WGM22: Waveform Generation Mode
Refer to TCCR2A.
Bits 2:0 – CS2[2:0]: Clock Select 2 [n = 0..2]
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 19-10. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkI/O/1 (No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/32 (From prescaler)
1 0 0 clkI/O/64 (From prescaler)
1 0 1 clkI/O/128 (From prescaler)
1 1 0 clkI/O/256 (From prescaler)
1 1 1 clkI/O/1024 (From prescaler)
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
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(b)
(i) For a pulse width modulated (PWM) signal varying from 0V to 5V, with
frequency 100Hz, what is the duration of the ON time of the waveform per period,
if an average value of 3.8V to be obtained by this PWM signal? (2 marks)
(ii) For a PWM signal obtained by Timer/Counter2 (relevant to the extraction of the
datasheet given above), if TCCR2A=0b11000011, TCCR2B=0b00000010,
OCR2A=63 and OCR2B=128, what is the frequency (in Hz) and duty cycle (as a
percentage) of the resulting PWM signal if the microcontroller clock frequency is
8MHz. (4 marks)
(iii) Write a C code segment to configure timer/counter 2 (relevant to the extraction of
the datasheet given above) to obtain a fast-PWM signal on OC2B pin (i.e. PD6
pin) in non-inverting mode, under the mode 7 in table 19-9 with a prescaler value
of 256 for clock division and 50% duty cycle. You can assume that the necessary
I/O register macro definitions are available. (4 marks)
2
4
4
Q6
/17
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Question 7. (14 marks)
(a) Consider the following assembly language code for Atmega324A and answer the
questions below in relation to the two-pass assembly process
jmp RESET
jmp ISR1
jmp ISR2
.dseg
var1: .BYTE 1
var2: .BYTE 4
var3: .BYTE 2
.cseg
.def temp=r16
table1: .DB 102,105,71,121,0
table2: .DB 60,35,86,8,39,46,0
RESET:
ldi temp, low(RAMEND)
out SPL, temp
ldi temp, high(RAMEND)
out SPH, temp
(i) list the different assembler directives, labels and assembly language instructions
found in the above code segment (3 marks)
(ii) What is the code segment size in bytes for the above code? (1 mark)
(iii) What is the data segment size in bytes for the above code? (1 mark)
(iv) At what program memory address, the instruction with the label RESET be
placed? (2 marks)
3
1
1
2
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(b) A Western Digital Ultrastar hard drive has the following specifications:
Nominal Capacity: 6TB (1TB = 1012 bytes)
Sector size: 4096 bytes
Rotational speed: 7200 RPM
Max Sustained transfer rate: 255MB/s (1MB = 106 bytes)
Average seek time (typical): 8.0ms (read) / 8.6ms (write)
The hard drive is formatted with a file system that has a block size of 16kB (16,384 bytes)
and currently contains 1,400,000 files of various sizes which occupy 100,000,000 data
blocks.
i) What is the average access time when writing to the disk? (Show your working.)
(1 mark)
ii) How much total space within the 100,000,000 allocated data blocks is likely to be
wasted (i.e. not used for storing data)? (Show your working. Express your answer in
kB, where 1kB=1024 bytes). (2 marks)
(c) In a certain system a CPU is interfaced with data memory having 236 bytes with an
addressable cell size of 16 bits. If the data bus width is 64 bits, what is the width of the
address bus? (2 marks)
(d) In a UART communication scenario where a transmitter sends 8 bits of data, with 1 start
bit, 2 stop bits, even parity bit at baud rate of 9600 bauds/sec, what is the associated bit
rate in this serial communication? (2 marks)
Final Question.
1
2
2
2
Q7
/14
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For scratch work/additional workings
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For scratch work/additional workings
END OF EXAMINATION