Semester One Examinations, 2023 CSSE2010/7201
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This exam paper must not be removed from the venue
Venue ____________________
Seat Number __________
Student Number |__|__|__|__|__|__|__|__|
Family Name ____________________
First Name ____________________
School of Information Technology and Electrical Engineering
Semester One Examinations, 2023
CSSE2010/7201 Introduction to Computer Systems
This paper is for St Lucia Campus students.
Examination Duration: 120 minutes
Planning Time: 10 minutes
Exam Conditions:
•This is an Open Book examination
•Casio FX82 series or UQ approved and labelled calculator only
•During Planning Time - Students are encouraged to review and plan
responses to the exam questions
•This examination paper will be released to the Library
Materials Permitted in the Exam Venue:
(No electronic aids are permitted e.g. laptops, phones)
* Open-book: Any additional written or printed material is permitted;
material may also be annotated.
Materials to be supplied to Students:
Additional exam materials (e.g. answer booklets, rough paper) will
be provided upon request.
None
Instructions to Students:
If you believe there is missing or incorrect information impacting
your ability to answer any question, please state this when writing
your answer.
Answer all questions in the space provided. Do not use red pen to
answer.
For Examiner Use Only
Question
Mark
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Total _________
Semester One Examinations, 2023 CSSE2010/7201
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Question 1. (15 marks)
(a) Perform the following number representation conversions and answer any subsequent
questions. Show your working.
(i) 3-digit hexadecimal number 0x91F to 4-digit octal and to decimal format. What is
the minimum number of D flip-flops required to store your answer? (2 marks)
(ii) 12-bit binary signed magnitude number 1000 0000 0111 to 12-bit binary ones
complement format. What is the range of both formats? (2 marks)
(iii) Decimal number (-118) to 8-bit binary two’s complement format (1 mark)
(iv) A programmer ordered “11011110110010101111 coffee” in binary. What did the
programmer order in hexadecimal? (1 mark)
(v) Express the decimal number (-131) in 9-bit excess-256 and two’s complement
formats. (2 marks)
8
Semester One Examinations, 2023 CSSE2010/7201
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(b) Consider the 8-bit binary two’s complement numbers A=00100011 and B=11011101.
(i) What is the result of A+B in 8-bit binary two’s complement format? Show your
working. Here, + indicates addition. (2 marks)
(ii) What are the values (0 or 1) of negative (N), zero (Z), carry (C) and overflow (V)
flags after completing the above 8-bit computation in (b)-(i)? (1 mark)
N: Z: C: V:
(c) Express the decimal number (-48.875) in 32-bit IEEE single-precision floating point
format. Show your working and express the final answer in 8-digit hex. (3 marks)
(d) Write down in 8-digit hex the representation of IEEE single-precision floating point of
the negative of the number in (c) above. (1 mark)
3
3
Q1
/15
1
Semester One Examinations, 2023 CSSE2010/7201
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Question 2. (12 marks)
Consider the logic diagram shown below and answer the following questions. , , , , , !, ", and ! are Boolean valued inputs and is a Boolean valued output.
(a) Complete the following truth table using , , , , (3 marks)
(b) What values need to be assigned to , , , , inputs to generate the desired
function Z = " ⋅ ! + X! ⋅ Y" ⋅ Y! at the output? (3 marks)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
3
3
Semester One Examinations, 2023 CSSE2010/7201
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(c) Considering the truth table for the given function in part (a), provide the unsimplified
sum-of-product (SOP) logic expression for , where each product term contains exactly
3 variables. (1 mark)
(d) Using Boolean algebra, show how you can simplify the above SOP expression for
in (c) into an expression given in (b) (1 mark)
(e) Draw the logic circuit for the expression in (b) using AND, OR and NOT gates.
(2 marks)
(f) Using a logic diagram, show how you can implement only using 2-input NAND
gates. Your solution must not contain more than 12 two-input NAND gates.
(2 marks)
2
Q2
/12
1
1
2
Semester One Examinations, 2023 CSSE2010/7201
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Question 3. (18 marks)
(a) Consider the state machine illustrated below. The machine’s purpose is to sort red and
green balls into their respective channels (R, G) using a circuit that you must design.
Following rules/assumptions apply to this system:
• The system is driven by an internal clock signal.
• The balls are stacked in the storage column with a fixed color and number pattern (2
red balls, followed by 3 green balls, followed by 2 red balls, followed by 3 green
balls etc.)
• Only one ball is released at the time by the mechanical valve.
• The mechanical valve is fully manual, meaning there is no circuitry involved. It is
also assumed that the valve cannot be opened again until the previously released ball
passed fully through either channel R or G, was registered by a detector and the
trap door orientation was adjusted.
• The detector has internal circuitry to produce a rising edge upon ball passing
through the channels. Therefore, the binary input to your circuit indicates the
presence of a rising edge on the input. Similarly, D indicates absence of a rising edge
on the input.
• A trap door is controlled by the circuit output. When the output of the circuit is set to
0, the trap door is opened, allowing the balls to fall through to channel R. Similarly,
when the output of the circuit is 1, the trap door is closed, and the balls go into
channel G. Assume the trap door opens and closes instantaneously.
• The system is initialized to = 0, meaning the trap door is lowered to let balls pass
through to R channel.
(i) Draw a Moore type finite state machine (FSM) state diagram to indicate the operation
of this ball sorting system ONLY for the given sequence of balls illustrated on the
Figure above and NOT for other ordering. Input causing state transitions should be
indicated using variable and state names such as S0, S1 etc. should be used rather
than encodings. State any assumptions you make. (5 marks)
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(ii) Provide a 2-D state table for your state diagram in (a)-(i). You do not need to
consider state encodings and you can use the same state names as in your state
diagram in (a)-(i). (5 marks)
(iii) How many D flip-flops do you need to implement this FSM under the following state
encoding schemes? Binary, Gray code, and One-hot encoding. (1.5 marks)
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(iv) How many invalid states do you get with state encodings and the number of D flip-
flops in (a)-(iii)? (1.5 marks)
(b) Consider the synchronous sequential circuit given below.
Complete the function table below to find the values of Q1 and Q0 outputs after 5 clock
edges, with other inputs as indicated in the table. Assume that the asynchronous active-
high SET and CLR inputs of the flip-flops are kept at low (i.e., not activated) during the
operation. (5 marks)
Clock edge number FN I1 I0 A Q1 Q0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 0
4 0 0 1 1
5 1 1 1 1
13
5
Q3
/18
Semester One Examinations, 2023 CSSE2010/7201
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Question 4. (8 marks)
Consider the ALU bit slice shown below (note that for the output multiplexer on the right
hand side, F2 is the most significant of the select bits, so for example, if F2,F1,F0 = 0,0,1
then input 1 of the multiplexer will be selected).
Consider 8 of these ALU bit slices put together to form an 8-bit ALU (i.e., with 8-bit data
inputs A and B). Complete the following table to show the required control inputs for the
ALU to perform the given functions. (Each control input will have value 0 or 1 or X (don’t
care). The “carry in” control input applies only to the least significant bit, the “carry in” input
of other bit slices comes from the “carry out” output of its neighbouring bit slice. The “right
shift in” control input applies only to the most significant bit; the “right shift in” input of
other bit slices comes from the “right shift out” output of its neighbouring bit slice.) If it is
not possible to generate the given function, make a comment to this effect below the table. If
there is more than one way to generate the given function, just show one way.
(2 marks each)
Description of
Function Output ENA INVA ENB INVB
Carry
In
Right
Shift
In F2 F1 F0
A divided by 2 (A is unsigned
and even)

̅ + 7 (bitwise NOR) 0 0 0
B 1 0 1
Constant value (-2)
in 2’s complement


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ϭ
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
KƵƚƉƵƚ
ZŝŐŚƚ^ŚŝĨƚKƵƚ ĂƌƌLJ/Ŷ
/Es
E
E
ZŝŐŚƚ^ŚŝĨƚ/Ŷ ĂƌƌLJKƵƚ
&Ϯ
&ϭ
&Ϭ
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Q4

/8
Semester One Examinations, 2023 CSSE2010/7201
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Question 5. (16 marks)
This question applies to the AVR ATmega324A microcontroller and associated assembly
language instructions.

(a) Write down the machine code corresponding to the AVR assembly language instruction.
ldi r25, 0xFF (1 mark)
(b) How many CPU cycles are required to execute code in (a) and what is the code size in
bytes in program memory? (1 mark)
(c) What is the binary value in register r31 and what are the status register bits Z, N, and
C after the execution of each of the following independent blocks of instructions. Assume
Z, N, and C are all initially 0 before the execution of the first instruction in each block.
(2 marks each)
(i) ldi r31, 0x36
inc r31
lsl r31
(ii) ldi r31, 0xD1
ldi r17, 46
or r31, r17
(iii) ldi r31, 0xD1
ldi r17, 0xD0
cp r31, r17
brge csse2010:
ldi r31, 16
jmp csse7201
csse2010:
ldi r31, 0xFF
csse7201:
mov r17, r31

(iv) ldi r31, 5
ldi r30, 7
push r31
push r30
push r31
pop r31
inc r31
pop r31
inc r30
pop r31



8
1
1
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(d) Initialise a 32-bit signed two’s complement variable stored in register pair Y:Z to (-128).
Here, Y register contains the most significant 16 bits of the number. How many bytes in
the program memory does your code occupy and how many CPU cycles does it take to
complete the execution? (3 marks)
(Code: 2 marks, code size: 0.5 mark, CPU cycles: 0.5 mark)
(e) The 8-bit signed two’s complement number A is stored in register r22. You want to
perform an operation A-5 and store the result back in r22. However, if the result is
negative due to the subtraction operation, the result stored in r22 should be made equal to
0x00. (3 marks)
Q5
/16
3
3
Semester One Examinations, 2023 CSSE2010/7201
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Question 6. (16 marks)
(a) Brisbane City Council is planning to use ATmega324A microcontroller to cycle between
different traffic states on a pedestrian crossing. You have been employed by the council
to write a function that will control the traffic light LEDs. The figure below illustrates
which LEDs correspond to car and pedestrian traffic lights, with some additional LEDs
to be used for error identification purposes.
Write a C function uint8_t update_traffic_lights(uint8_t state)for
Atmega324A device to display the correct LED pattern based on an 8-bit integer input
argument called state. Consider the following points.
• The function has an 8-bit integer argument called state and an integer return value
• LEDs L0-L7 are connected to pins A0-A7 of port A. A logic HIGH on a pin will
turn ON the corresponding LED.
• The function should configure port A pins appropriately.
• The function should output the correct LED pattern to port A pins based on the
input argument state and return as follows:
o state = 0 à Car LED Red, Pedestrian LED Green and return 0
o state = 1 à Car LED Orange, Pedestrian LED Green and return 0
o state = 2 à Car LED Green, Pedestrian LED Red and return 0
o state = 3 à Car LED Orange, Pedestrian LED Orange and return 1
o state = 4 à Only Error LEDs ON and return 2
(8 marks)
uint8_t update_traffic_lights(uint8_t state){
} 8
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The following is extracted from Section 17.11 of the ATmega324A datasheet related to
Timer/Counter 2. You will need to refer to this information when answering question 6(b).
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Semester One Examinations, 2023 CSSE2010/7201
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Question 6 (continued)
(b) A company making LED camping flashlights wants to implement brightness control into
their latest product portfolio. The company asks you to write a function on ATmega324A
microcontroller that controls the brightness of an LED from level 0 to 255.
Write a C function void set_LED_brightness(uint8_t
brightness_level)that implements such functionality using the timer/counter 2 in
fast PWM mode, using non-inverting mode with the TOP set to 0xFF and prescaler set to
256. Connect the LED to the output compare A pin (OC2A). The function needs to
configure the port A appropriately. (5 marks)
What is the period (in seconds) and frequency (in Hz) of the PWM signal driving the
LED? What is the brightness_level value if the duty cycle is 25%? (3 marks)
uint8_t set_LED_brightness(uint8_t brightness_level){
}
Q6
/16
8
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Question 7. (15 marks)
(a) Consider the following assembly language code module for Atmega324A and answer the
questions below in relation to the two-pass assembly and linking processes.
.include "m324Adef.inc"
.equ dog_count = 13
.equ cat_count = 10
.equ other_count = 5
jmp load_values
.dseg
var1: .BYTE 14
var2: .BYTE 13
.cseg
.def temp0 = r20
.def temp1 = r21
.def temp2 = r22
.def total = r16
animal_counts: .DB dog_count, cat_count, other_count
vars: .DW var1, var2
load_values:
ldi temp0, dog_count
ldi temp1, cat_count
ldi temp2, other_count
jmp calc_total
calc_total:
clr total
add total, temp0
add total, temp1
add total, temp2
(i) What is the code segment size in instruction words for the above module? (1 mark)
(ii) What is the data segment size in bytes for the above module? (1 mark)
1
1
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(iii) If the code segment and data segment location counters for the above module start from
0 and 256, respectively, complete the following symbol table for the assembly process
(3 marks)
Symbol Segment Address
var1
var2
animal_counts
vars
load_values
calc_total
(iv) The module shown above (which is now called module B) is linked with two other
assembled modules A and C with code and data segment sizes shown below.
Module Code segment size
(instruction words)
Data segment size
(bytes)
A 13 20
C 35 28
If the modules are linked in order A, B, C starting from code segment address 0x44 (68
decimal) and data segment address 0x100 (256 decimal), determine the code and data
segment relocation constants (in decimal) for all modules. (3 marks)
Module A Module B Module C
Code Segment Relocation Constant
Data Segment Relocation Constant
(v) After linking as described in (iv), provide the new relocated memory addresses for
symbols animal_counts and var1 in the symbol table from (iii) (2 marks)
(b) In a UART communication scenario a transmitter sends 6 bits of data with 1 start bit, 2
stop bits, and even parity bit at a bit rate of 69,120 bits/sec.
(i) What is the associated baud rate in this serial communication? Show your working.
(1 mark)
(ii) If the content of the UART frame is 1010110111, where MSB is the start bit and
even parity bit is LSB, what is the decimal value send over UART?
(2 marks)
3
3
2
1
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(iii) Considering the above UART frame in (b)-(ii), should the receiver configured for
even parity communication trust the value received? Justify your answer. (2 marks)
2
2
Q7
/15
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For scratch work
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For scratch work
END OF EXAMINATION