CSSE2010-7201 Final Exam Answers 2018 Semester one
Page 1 of 13
Question 1. (11 marks)
(a) Consider the decimal number 173. Write down the octal representation of this number.
(1 mark)
255 or 0255 or 2558
(b) Consider the 8-bit binary number 10110110. Write down the decimal value of this
number if the number is considered to have each of the following representations.
(1 mark each)
i) 8-bit two’s complement
– 74
ii) 8-bit unsigned
182
iii) 8-bit ones’ complement
– 73
iv) 8-bit excess-127
55
(c) Write down (in hexadecimal) both the IEEE single-precision and double-precision
floating-point representations of 65.375. Show your working. (4 marks)
65.375 is positive so the sign bit is 0
65.375 = 64+1+0.25+0.125
In binary this is 1000001.011 which can be rewritten as 1.000001011 x 26
The exponent is 6, which in 8-bit excess-127 representation is 10000101 (133).
The mantissa (after the binary point) is 000001011
The single precision IEEE floating point binary representation is therefore
0 10000101 00000101100000000000000 (23 bits in mantissa)
when grouped in 4-bit groups, this is
0100 0010 1000 0010 1100 0000 0000 0000
In hexadecimal this is 4282C000
For the double precision representation, the exponent (6) in excess-1023 format is
10000000101 (1029)
The double precision IEEE floating point binary representation is therefore
0 10000000101 000001011000 … 000 (52 bits in mantissa)
When grouped in 4-bit groups, this is
0100 0000 0101 0000 0101 1000 0000 … 0000
In hexadecimal this is 4050580000000000 (16 digits)
(d) Consider the 8-bit two’s complement binary numbers 01011100 and 01101010.
i) What is the result (in 8-bit binary) of adding these two numbers? (1 mark)
11000110
ii) What would be the values (0 or 1) of the V (overflow), C (carry), N(negative)
and Z (zero) flags after the addition operation in (i) above? (1 mark)
V: 1_ C: 0 N: 1 Z: 0_
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 2 of 13
Question 2. (12 marks)
(a) Consider the logic function = . ' + . (⨁)----------------------
i) Draw a logic circuit which implements this function. (2 marks)
Any answer logically equivalent to this is also acceptable.
ii) Complete the following truth table for X. (2 marks)
A B C X
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
iii) Write down a sum-of-products expression for X. (2 marks)
X = ̅. & + ̅. ̅ + . . or ̅. ). ̅ + ̅. ). + ̅. . ̅ + . .
or ̅. ) + ̅. . ̅ + . . or ̅. ̅. +̅. ). + . .
Or any other logically equivalent sum of products expression.
(b) Consider the logic function = ( + & ). + & .
i) Draw a circuit which implements Y from inputs A, B, C and D using only two-input
NAND gates. (2 marks)
Or any other logically equivalent circuit that only uses 2-input NAND gates.
ii) Draw a circuit schematic which implements Y using only the IO Board and chips from
the 74 series logic chips used in the learning labs in this course. The inputs A and B
should come from IO Board switches, inputs C and D should come from IO Board push-
buttons and the output (Y ) should be shown on an IO Board LED. (4 marks)
Sample solution – others are possible.
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 3 of 13
Question 3. (10 marks)
(a) Draw the logic diagram for a 3-bit synchronous counter which counts through the
sequence 000 à 010 à 101 à 001 à 110 à 000 à… .
Show all your working. (4 marks)
Q2 Q1 Q0 D2 D1 D0
0 0 0 0 1 0
0 0 1 1 1 0
0 1 0 1 0 1
0 1 1 X X X
1 0 0 X X X
1 0 1 0 0 1
1 1 0 0 0 0
1 1 1 X X X
One possible set of equations:
One possible circuit:
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 4 of 13
Question 3. (continued)
(b) Draw a state diagram which implements the following toll gate behaviour. The toll gate accepts only one
and two dollar coins and five dollars (or more) must be received to open the gate. No change is given. There
are two inputs S and T:
- S=1 indicates a one dollar coin has been received (0 otherwise); and
- T=1 indicates a two dollar coin has been received (0 otherwise)
Note that it is possible to receive both simultaneously.
There are eight outputs:
- A,B,C,D,E,F,G – which are the bits of a standard seven segment display; and
- OPEN – which is 1 when the gate is to be opened (sufficient money has been received) and 0
otherwise.
When some, but insufficient, money has been received, the seven segment display shows how much money
has been received (in dollars). The display is blank otherwise. (6 marks)
Inputs: S,T Outputs: A,B,C,D,E,F,G,OPEN
It’s OK if all transitions from state 5 (those shown in blue) instead go back to state 0 – i.e. assume we
go back to reset before accepting coins – it wasn’t clear in the specification what happens after the toll
gate opens.
Every input combination (ST=00,01,10,11) must be covered exactly once by the transitions from every
single state.
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 5 of 13
Question 4. (13 marks)
Consider the ALU bit slice shown below. [Note that for the output multiplexer on the right
hand side, F2 is the most significant of the select bits, so for example, if F2,F1,F0 =0,0,1 then
input 1 of the multiplexer will be selected.]
(a) Consider 16 of these ALU bit slices put together to form a 16-bit ALU (i.e. with 16-bit data inputs
A and B). Complete the following table to show the required control inputs for the ALU to
perform the given functions. (Each control input will have value 0 or 1 or X (don’t care). The
“carry in” control input applies only to the least significant bit, the “carry in” input of other bit
slices comes from the “carry out” output of its neighbouring bit slice. The “right shift in” control
input applies only to the most significant bit; the “right shift in” input of other bit slices comes
from the “right shift out” output of its neighbouring bit slice.) If it is not possible to generate the
given function, make a comment to this effect below the table. If there is more than one way to
generate the given function, just show one way. (1.5 marks each)
Description of
Function Output ENA INVA ENB INVB
Carry
In
Right
Shift
In F2 F1 F0
(i) . & (bitwise) – either
answer is OK
1 0 1 1 X X 0 0 0
1 1 1 0 X X 0 1 1
(ii) B multiplied by 2 0 1 1 0 0 X 1 0 0
(iii) Logical shift right of A 1 0 X X X 0 1 1 0
(iv) & ⊕ (bitwise) Can’t be implemented.
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 6 of 13
Question 4. (continued)
(b) Consider a 16-bit binary number stored in AVR registers r5:r4. (r5 holds the most
significant byte, r4 holds the least significant.) Write down a sequence of AVR assembly
language instructions which perform each of the following operations. The result should
end up in r5:r4. Other registers can be used freely if required.
i) Sets r5:r4 to the constant unsigned value +1. (2 marks)
clr r5
clr r4
inc r4
Another option:
clr r5
ldi r16,1
mov r4,r16
ii) Multiplication of r5:r4 by –3 if the value in r5:r4 is considered to be signed (two’s
complement). (3 marks)
; First do multiply by 3
mov r14, r4
mov r15, r5 ; original value now saved to r15:r14
lsl r4
rol r5 ; r5:r4 now has 2 x original value (could do
; add followed by adc to do this also)
add r4,r14
adc r5,r15 ; r5:r4 now has 3 x original value
; Now do negation
ldi r16,1
clr r17 ; r17:r16 has 16 bit value of 1
com r4
com r5 ; flipped all bits of r5:r4 – now add 1
add r4,r16
adc r5,r17 ; now have original value x -3

16-bit negation of r5:r4 can also be done with negs as follows:
clr r0
neg r5
neg r4
sbc r5, r0
iii) Division of r5:r4 by 16 if the value in r5:r4 is considered to be unsigned. (2 marks)
One answer:
lsr r5
ror r4
lsr r5
ror r4
lsr r5
ror r4
lsr r5
ror r4
Another possibility – using swap instruction
ldi r16, 0x0F
swap r4
and r4, r16 ; bottom four bits of r4 now in place
and r16, r5 ; bottom four bits of r5 copied to r16
swap r16 ; bottom four bits of r5 now in top half of r16
or r4, r16 ; r4 now complete
ldi r16, 0x0F
swap r5
and r5, r16 ; r5 now complete
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 7 of 13
Question 5. (11 marks)
This question applies to the AVR ATmega324A microcontroller.
(a) Write down the machine code corresponding to the AVR assembly language instruction
sbrs r17, 5 (1 mark)
Opcode template is 1111 111r rrrr 0bbb where rrrrr = register number and bbb= bit number. Answer:
1111 1111 0001 0101 (or hex FF15)
(b) What will be the binary value in register r30 and the status register bits Z, N, and C after
the execution of each of the following independent blocks of instructions. Assume Z, N
and C are all initially 0 before the execution of the first instruction in each block. If there
is insufficient information to determine the value of a bit then indicate this with a
question-mark (?) in the relevant box. (2 marks each)
i) ldi r30, -128
dec r30
ii) ldi r30, 0321 11010001 in binary
lsl r30
iii) ldi r30, 0xAC
andi ZL, 0xCA
iv) ldi r30, 0x5F Note memory address 0x5F is SREG
clr r31
st Z+, r30 Note Z register (i.e. ZL) is incremented
v) ldi r30, 7
push r30
in r31, SREG
or r31, r30
push r31
pop r30
out SREG, r30
r30: 0 1 1 1 1 1 1 1 Z: 0 N: 0 C: 0
r30: 1 0 1 0 0 0 1 0 Z: 0 N: 1 C: 1
r30: 1 0 0 0 1 0 0 0 Z: 0 N: 1 C: 0
r30: 0 1 1 0 0 0 0 0 Z: 1 N: 1 C: 1
r30: ? ? ? ? ? 1 1 1 Z: 1 N: 1 C: 1
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 8 of 13
Question 6. (10 marks)
(a) What will be printed after the execution of each of the following C code fragments?
(1 mark each)
i) int16_t x = -25;
int16_t y = 4;
x += 3 << --y;
printf("%d %d", x, y);
ii) int8_t x = 0x70; 112 decimal
int8_t y = 070; 56 decimal
x += y; 168 – but wraps around so -88
printf("%d", x);
iii) int16_t i = 22;
int16_t b = 7;
while(i > b) {
i -= 2;
b = b^i;
}
printf("%d %d", i, b);
(b) Write a C declaration which declares var to be an array of thirty-two 16-bit unsigned integers
(1 mark)
One of
uint16_t var[32];
unsigned short var[32];
unsigned int var[32];
(c) For each of the following C statements for the Atmel AVR ATmega324A, write down the
assembly language equivalent. (You may assume that definitions in the m324Adef.inc file
are available. Several instructions may be required.)
i) DDRC ^= 0x0F; (1 mark)
in r1, DDRC ; could be lds r16, 0x27 or in r16, 7
; can use another register besides r1
ldi r17, 0x0F
eor r1, r17
out DDRC, r1
ii) OCR2A = 48; (1 mark)
ldi r16, 48
sts OCR2A, r16 ; or sts 0xB3, r16
iii) TCNT1 = TCNT0; (1 mark)
in r1, TCNT0 ; or in r1, 0x26 or lds r1, 0x46
clr r2
sts TCNT1L, r1 ; or sts 0x84, r1
sts TCNT1H, r2 ; high byte zero – or sts 0x85, r2
-1 3
-88
16 17
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 9 of 13
Question 6. (continued)
iv) DDRA = 0x0F;
PORTA = (ICR1 >> 12); (1 mark)
ldi r16, 0x0F
out DDRA, r16 ; or out 0x01, r16 or sts 0x21, r16
lds r16, ICR1H
swap r16
andi r16, 0x0F
out PORTA, r16 ; or out 2, r16 or sts 0x22, r16
v) uint8_t tmp;
if(ADMUX & (1 >> ADLAR)) {
tmp = ADC >> 8;
} else {
tmp = ADC >> 2;
}
PORTB = tmp; (2 marks)
(The question was originally intended to use << ADLAR rather than >> ADLAR.)
Option one (code as written):
lds r16, ADMUX ; or lds r16, 0x7C
andi r16, (1>>ADLAR) ; or andi r16, 0 or andi r16, (1>>5)
breq else
; not equal to zero
lds r16, ADCH ; or lds r16, 0x79
rjmp done ; or jmp
else:
lds r16, ADCH ; or lds r16, 0x79
lds r17, ADCL ; or lds r16, 0x78
lsr r16
ror r17
lsr r16
ror r17
done:
out PORTB, r17 ; or out 5,r16 or sts 0x25,r16
Option two (optimise out the branch of the if statement never executed because 1>>ADLAR is 0):
lds r16, ADCH ; or lds r16, 0x79
lds r17, ADCL ; or lds r16, 0x78
lsr r16
ror r17
lsr r16
ror r17
out PORTB, r17 ; or out 5,r16 or sts 0x25,r16

Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 10 of 13
Question 7. (14 marks)
The following is an edited extracted from Section 19.11 of the ATmega324A datasheet. You
will need to refer to this information when answering this question. (Omitted from answers.)
(a) Write a C function
uint8_t configure_pwm(uint8_t prescale, uint8_t dutycycle)
for the AVR ATmega324A microcontroller. The function configures Timer/Counter 2 for
Fast PWM output, repeatedly counting from 0 to 255 based on a prescaled clock (as
determined by the prescale argument) with output pulses on pin OC2A (port D, pin 7).
The function takes two arguments:
- prescale – which should be from 1 to 7 inclusive – corresponding to clock prescale
dividers 1,8,32,64,128,256 and 1024 respectively; and
- dutycycle – a value from 0 to 100 which indicates the (approximate) percentage of
time that pulses should be high.
The function must return 1 and do nothing if arguments are outside the expected ranges,
otherwise it configures the timer and the output pin and returns 0. State any assumptions
you need to make as comments in the code. (7 marks)

uint8_t configure_pwm(uint8_t prescale, uint8_t dutycycle)
{
if(prescale < 1 || prescale > 7 || dutycycle > 100) {
return 1;
}
DDRD |= 0x80; // set port D pin 7 to be an output
TCCR2B = prescale;
TCCR2A = 0b10000011; // bits COM2A1, WGM21, WGM20
OCR2A = dutycycle * 256 / 100;
return 0;
}
(b) Assuming that timer/counter 2 is configured as described in Question 7(a), write an AVR
assembly language interrupt handler for the ATmega324A that will be called when
timer/counter 2 overflows. The handler must set the width of the next pulse based on the
value read from the port B pins. If the value (interpreted as an unsigned number) is 0 or
255, the interrupt handler should do nothing, otherwise the handler should set the width of
the pulse (i.e. the number of prescaled clock cycles the pulse is high (1) for) to be the
value read from the port B pins. The interrupt handler must preserve the values of all
general-purpose registers and the status register (i.e. these register values must be restored
to their original values if they are changed by the handler). (7 marks)
handler:
// Save registers that we use
push r16
in r16, SREG
push r16
in r16, PINB
cpi r16, 0
breq done
cpi r16, 255
breq done
sts OCR2A, r16 ; or sts 0xB3, r16
done: pop r16
out SREG, r16
pop r16
reti
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 11 of 13
Question 8. (8 marks)
Consider the following AVR ATmega324A assembly language module (omitted from
answers) and answer the questions on the following page.
(a) What is the overall size (in instruction words) of the code segment for this module?
(1 mark)
Give one mark if correct, zero otherwise.
(b) What is the overall size (in bytes) of the data segment for this module? (1 mark)
Give one mark if correct, zero otherwise.
(c) The module shown above (which we will now call module C) is linked with three other
modules (A, B and D) with code and data segment sizes as shown:
Module Code segment size
(instruction words)
Data segment size
(bytes)
A 56 44
B 127 96
D 93 10
If the modules are linked in order A, B, C and D starting from code segment address 0x3E
(62 decimal) and data segment address 0x100 (256 decimal), determine the code and data
segment relocation constants (in decimal) for all modules. (4 marks)
Module A Module B Module C Module D
Code Segment Relocation Constant 62 118 245 295
Data Segment Relocation Constant 256 300 396 526
(d) After linking as described in (c), at what memory address (in decimal) will the variable
bytes_in_output_buffer be found? (1 mark)
(e) After linking as described in (c), at what instruction word address (in decimal) will the
instruction at label loop be found? (1 mark)
50
130
523 (127 bytes into module D)
254 (9 words into module C)
7
Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 12 of 13
Question 9. (11 marks)
(a) The Seagate ST8000DM002 hard drive has the following specifications:
Nominal Capacity: 8TB (1TB = 1012 bytes)
Guaranteed Sectors: 1,953,506,646 (at sector size of 4096 bytes)
Rotational speed: 7200 RPM
Max Sustained transfer rate: 225MB/s (1MB = 106 bytes)
Average seek time (typical): 8.5ms (read) / 9.5ms (write)
The hard drive is formatted with a file system that has a block size of 16kB (16,384 bytes) and
currently contains 600,000 files of various sizes which occupy 40,000,000 data blocks.
i) What is the average access time when writing to the disk? (Show your working.) (2 marks)
Average access time = average seek time + average rotational latency
= 9.5ms + rotation time/2
= 9.5ms + (60/7200)/2 s
= 9.5ms + 4.17ms
= 13.67ms
ii) If the block size were 8kB (8,192 bytes) instead of 16kB, how many data blocks would you
expect to be occupied by files? (Show your working.) (2 marks)
It is expected that half the files would use less than half their last 16kB data block.
Number of blocks = 80,000,000 – 0.5 x 600,000 = 79,700,000
iii) If the file system overhead is 8% of the total disk capacity, how many additional files of size
40kB (40 x 1024 bytes) could be saved on the disk? (Show your working.) (2 marks)
Total blocks on disk = (8 x 1012 / 16,384) = 488,281,250 (or 488,376,661 – based on guaranteed
sectors number divided by 4 then rounded down)
File system overhead = 8%, i.e. 0.08 x 488,281,250 = 39,062,500 blocks (or 39,070,132 or
39,070,133)
Available blocks = 488,281,250 – 39,062,500 – 40,000,000 = 409,218,750
OR Available blocks = 488,376,661 – 39,070,132 (or 3) – 40,000,000 = 409,306,528 (or 9)
Each file of size 40kB will occupy 3 blocks, so the number of additional files of this size which could
be saved = 409,218,750 / 3 = 136,406,250
OR 409,306,528 (or 9) / 3 = 136,435,509

Semester One Final Exam Answers, 2018 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 13 of 13
Question 9. (continued)
iv) The hard disk is connected to a computer via a USB 2.0 interface. Approximately
how long will it take to copy all 600,000 files from the disk? (Show your working.
State all assumptions.) (2 marks)
The amount of data to be transferred is 40,000,000 blocks = 40,000,000 x 16,384 bytes =
655,360,000,000 bytes
(or could allow for wasted space at end of each file (average half block per file), i.e. 655,360,000,000
– 600,000 x 8,192 = 655,360,000,000 – 4,915,200,000 = 650,444,800,000 bytes
The maximum USB 2 transfer rate is 480Mbps = 60MBps (slower than max sustained disk transfer
rate so disk limit is not an issue). You may use this number or may assume that the max transfer rate is
approximately 50% of this amount (e.g. 30MBps). Other reasonable assumptions OK.
Time = Data / transfer rate
Data to be transferred (bytes) Transfer Rate (Mbyte/sec) Answer
655,360,000,000 60,000,000 10923s (182min)
655,360,000,000 30,000,000 21845s (364min)
650,444,800,000 60,000,000 10841s (181min)
650,444,800,000 30,000,000 21681s (361min)

(b) Consider a little-endian computer with a memory which has an addressable cell size of
one byte and which doesn’t require natural alignment. The values in memory cells 272 to
280 inclusive are as shown in the table below.
i) What 16-bit two’s complement value is stored at address 278? Give your answer as a
decimal number. (2 marks)
Hex value is 8897. Binary is 1000 1000 1001 0111. Converting this to decimal:
-32,768 + 2048 + 128 + 16 + 4 + 2 + 1 = -30,569
ii) If the computer stores the 32-bit unsigned value 0x20107201 to address 275, show
the contents (in hexadecimal) of the memory cells which are changed by this
operation. (1 mark)
Initial Value (hexadecimal) New Value (if changed)
272: F1
273: 2E
274: D3
275: 4C 01
276: B5 72
277: 6A 10
278: 97 20
279: 88
280: 79