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Lab 1 Manual:
Introduction to Digital VLSI Circuit Design
using Cadence Virtuoso
University of Bristol
School of Electrical, Electronic, and Mechanical Engineering
Dr Faezeh Arab Hassani
January 2024
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Table of Contents
1 Preamble ................................................................................................. 3
1.1 Intended Learning Objectives & Outcomes .............................................. 3
1.2 Confidentiality of Process Information..................................................... 4
1.3 How to Read the Lab Documents and Complete the Exercises ................. 4
1.4 Introduction to Unix/Linux ...................................................................... 6
1.5 Acknowledgements.................................................................................. 9
2 Introduction to Cadence........................................................................ 9
2.1 Configuring Your Unix Environment for Cadence ................................... 9
Task 2.1: Setting Unix Environment for Full-Custom Design --------------------------------- 10
2.2 Using the Cadence Documentation ........................................................ 13
2.3 Cadence Design Flow ............................................................................ 13
2.4 Running Cadence in Subsequent Lab Sessions ....................................... 14
3 Schematic Entry ................................................................................... 15
3.1 Creating a New Library ......................................................................... 15
Task 3.1: Create a New Library --------------------------------------------------------------------- 15
3.2 Designing an Inverter............................................................................. 16
Task 3.2: Adding a Cell to the Library ------------------------------------------------------------- 17
3.3 Creating a Symbol for the Inverter Schematic ........................................ 22
Task 3.3: Creating an Inverter Symbol ------------------------------------------------------------ 22
3.4 Creating a Test Bench ............................................................................ 23
Task 3.4: Create a Testbench Schematic ---------------------------------------------------------- 23
3.5 Running a Simulation ............................................................................ 25
Task 3.5: Running a Transient Simulation ------------------------------------------------------- 26
Task 3.6: Observing the Effect of Transistor Sizing --------------------------------------------- 29
Exercise 3.1: Calculate the Equivalent Resistance of Minimum-sized Transistors --------- 29
Exercise 3.2: Calculating the Effect of Transistor Sizing --------------------------------------- 30
Confidentiality of AMS Hit-Kit --------------------------------------------------------------------- 31
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1 Preamble
1.1 Intended Learning Objectives & Outcomes
Learning Objectives
· To introduce the user to the Cadence design environment and the Virtuoso toolset
· To introduce digital full-custom design practices from schematic entry to analogue simulation
Learning Outcomes
By the end of this lab students should be able to:
· Manage basic tasks in the Unix Operating System necessary for using Cadence
· Launch Cadence and use the Virtuoso toolset
· Create circuit-level schematics using transistors and passives and carry out transient simulations
Labs 1 through 3 comprise a tutorial-based introduction to full-custom IC design based on the Cadence
toolset and the 0.35 m CMOS process from AMS. It covers three main areas: circuit design using
schematic entry (Lab 1), layout (Lab 2) and advanced simulation and verification techniques (Lab 3).
• These labs are complementary to the lectures.
• Please feel free to print the lab manuals if it is easier to move back and forth between sections.
• Texts with underlines have embedded links.
• Click on the symbol to go back to the previous place. For figures, symbols take you
back to the first time that the figure is mentioned within the text, you can click on symbols
to switch to other places that are referring to the same figure. Click on to return to the
Table of Content.
• It would be easier if you set the pdf view to ‘Fit One Full Page’ or with a zoom view below
100%.
Note:
• Attendance at the scheduled lab sessions (timetable is provided on Blackboard) is
MANDATORY in sessions attended by the lecturer and lab demonstrators. If you cannot attend
any of these for some compelling reason, please see me in good time. Please note that each lab
is a prerequisite for the next one.
• You must work alone on these assignments. Please note that plagiarism of any sort is an academic
offence.
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1.2 Confidentiality of Process Information
To do meaningful, industrially relevant work, these laboratory exercises use a physical design kit (PDK)
for a 0.35 mm technology called the Hit-Kit (short for High Performance Interface Tool Kit) from a
commercial vendor called AMS that is supplied under a Non-Disclosure Agreement (NDA).
All AMS supplied models, library files, datasheets and documentation made available to you can strictly
be used only to carry out design and simulation tasks prescribed in this Unit at the University of Bristol. No
information related to the AMS design kit may be disseminated to anybody or used for any purpose other
than the above. In addition to AMS supplied models, library files, datasheets and documentation, publishing
simulation results based on AMS device models or standard cells that allow comparisons to be made against
other processes is not permitted under the NDA.
You can only start these labs if you consent to the requirements of the NDA. By continuing you agree to
abide by the statement on the last page, which you must sign and upload to Blackboard by the
suggested deadline.
1.3 How to Read the Lab Documents and Complete the Exercises
These labs are individual exercises, i.e., you must work through them on your own, not in a group. Every
lab document is meant to be read through in order from beginning to end, and no section should be skipped.
Questions are embedded in each section, and are of two types:
- Tasks, where you should follow a series of instructions, such as completing a command in the
simulator.
- Exercises, where you are expected to produce some output, whether it is a worked calculation, a
circuit schematic, a simulation, or some discussion.
You will be marked on Exercises, and solutions should be uploaded electronically through Blackboard.
Each exercise will have specific instructions on what and how to submit. For more information refer to:
What you need to upload to Blackboard.
Important coursework submission deadlines:
1. Exercises in Lab 1 and Lab 2 manuals should be submitted to Blackboard as Coursework 1:
Cadence Schematic and Layout (Total 100 points, 30% of your final mark for both EENG 34050
and EENG M4050 students) by 13:00 on Thursday 29 February 2024. The submission point on
Blackboard will be opened 2 weeks before the deadline.
2. Exercises in Lab 3 manual should be submitted in Blackboard as Coursework 2: Cadence
Analysis (Total 100 points, 20% of your final mark for EENG 34050 students and 30% of your
final mark for EENG M4050 students) by 13:00 on Thursday 25 April 2024. The submission point
on Blackboard will be opened 2 weeks before the deadline.
During the lab sessions, the lecturer and lab demonstrators will ask you to show your work.
Please make sure to upload the required documents for each coursework by the deadlines. Penalty marks
will be considered for delayed submissions.
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Academic Integrity and Avoiding Plagiarism
Plagiarism is the act of trying to pass off somebody else’s work either wholly or in part as your own and is
an academic offence. Simply put, it is cheating and includes copying the answers to questions and
submitting any work electronically that is not exclusively your own. As these are individual assignments,
it is not permitted to:
- Discuss the answers to questions within a group and submit the same solution, possibly with minor
variations. If you do, it will be discovered, and all parties will receive zero for that question at a
minimum.
- Ask a lab demonstrator for the answer to an assessed question. The point of an assessed question is
to test your understanding, not the lecturer’s and lab demonstrators’ understanding.
Every submission for any assessed assignments must be completely your own effort. Discussions are a great
way of tackling new concepts and are an essential part of learning. However, it is not acceptable to provide
the same answer to individual exercises by working as a group. You should attempt the solution to the tasks
and exercises on your own, and not show each other your attempt.
Note:
• Carefully read the section on Academic Integrity.
• All students who collude on exercises and assignments will get zero marks for that bit of
coursework at a minimum, regardless of who copied from whom.
• Please do not ask the lab demonstrators to do exercises for you, or if an answer is correct. Their
task is to help you with Cadence. As an example, in Exercise 3.1, the only help you should ask
for from the demonstrators is on how to extract the delay from the simulated waveforms (if you
need to), not with the equivalent circuits, deriving an expression for the delay, or calculating the
equivalent resistances based on your simulation results. I cover all concepts in teaching sessions
and please do ask me if you need help.
Laboratory Usage
The 2.11 Linux lab is reserved for students of the VLSI Design course every Tuesday, from 10:00-13:00.
Please pick a seat, avoid walking about as much as possible, and keep conversation to a minimum to avoid
disturbing your colleagues. This is a centrally managed teaching resource, and all users must respect
the rules related to not consuming food and drink inside the lab as signposted at the entrance. If you
need a break, please use the resources provided in the foyer.
Remote Access to Linux Machines for Using Cadence
Follow the instructions in Task 2.1.

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1.4 Introduction to Unix/Linux
Many of you will be familiar with the Linux flavour of Unix and if that is the case simply skip this section.
If you do not have any experience with Unix, it is a good idea to go through a basic introductory tutorial,
to perform basic Operating System-related tasks such as listing the contents of a directory, copying and
moving files, reading text files, and understanding which configuration files modify which aspect of your
environment. Many such tutorials are freely available on the internet. A good one is available here:
http://www.ee.surrey.ac.uk/Teaching/Unix/.
Note:
• If you do not have experience with Unix, the basic commands below will allow you to do the rest
of the lab. It is strongly recommended that you follow some online tutorials afterwards. Spending
an hour or two understanding Unix will greatly benefit you in the long term.
For your reference, some basic commands are listed in Table 1. Bear in mind that Unix is case-sensitive.
All Unix commands listed below that you can type in are given in the format of “command arg” using
quotes and a different font. That is, you can type in the text inside the quotes.
Note:
• The Unix help is documented in man pages. You can get more information about any of the
following commands by typing “man command” at the command prompt. For example, “man
ls” will give you the man page for the command “ls”.
TABLE 1. Unix commands
Command Description
passwd Allows you to change your password. (Please follow standard University guidelines in managing
passwords and make sure that you use a secure password, and do not share it with anyone.)
ls Lists the files in your current directory. Most Unix commands take one or more optional
parameters, specified with a leading ‘−’ without the quotes. For example, “ls -l” lists your
files in the 'long format', which contains lots of useful information such as the exact size of the
file, the owner of the file, who has the right to read, write and execute, when it was last modified
etc.
“ls -a” lists all files, including file names that begin with a leading dot, which are typically
used for various configuration uses, and are not shown by default.
“ls -al” shows all files in long format.
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pwd Shows your current directory.
cd Changes directory to the directory . If such a directory does not exist, you will get an
error message. Here can contain a full path. You should bear in mind that paths in
Unix are specified with a forward slash rather than a backward slash as in Windows. For example,
you move to the root directory by specifying “cd /”. The Cadence installation directory is
/usr/local/cadence. You can move to this directory by typing “cd
/usr/local/cadence” from anywhere since you specify the full path.
When you log in, you always start out in your 'home directory', which is the directory allocated
to you as a user. You can always return to your home directory by typing “cd” without
arguments.
“cd ..” will move you one level up from your current position. You can use the tilde sign
‘~’ followed by a username as a shortcut to that user’s home directory. For example, “cd
~user1” will change to user1’s home directory. The ‘~’ sign on its own without a username
signifies your own home directory. The use of the tilde sign is permitted with any command that
uses a path, such as “ls” or “cp”.
mkdir Creates a directory called dirname.
cp
Copies to . This command also accepts wild cards. For example, the
command “cp /dir1/dir2/*” will copy all files contained in “/dir1/dir2” to
the current directory. The asterisk is a wild card signifying all files, and the dot (period)
at the end says to copy the files to the current location. If the directory being copied has
sub-directories, and you want to copy all these sub-directories, the option “-r” needs
to be used. So, for example, typing “cp -r ~user1/design ~/” will copy
the directory “~user1/design” (assuming you have read permission on it) and
all its contents including sub folders to your home directory.
rm Deletes the file . Bear in mind that Unix does not have a trash can or an undo function,
and anything deleted is deleted forever! It is wise to use the option “rm -i”, which will ask
you for confirmation before deleting anything. “rm” is a very powerful command, and “rm -
r” will remove directory contents recursively. For example, “rm -r myName” will remove
the directory myName and all its contents, including sub directories. Again, there is no recovery
once something is deleted, so always make a habit to use rm with the option −i. For example,
“rm -i myName” will prompt before trying to delete myName.
mv
Equivalent to “cp ” followed by “rm
”.
rmdir Deletes the directory if it is empty. “rmdir” deletes only empty directories.
more Shows the contents of , formatted to fit whatever size your xterm is. (You will see
machine code symbols if the file is not a text file.) Hitting the space bar will move onto the next
‘page’, while pressing ‘q’ will exit the command.
less More or less the same as “more” (!) except that “less” allows you to scroll using scrollbars.
Also quitting the command will not retain any text in your xterm, while “more” will retain the
contents of the last page.
vi Starts the vi text editor. This is a lightweight text editor that is standard with all Unix installations.
Please check this link https://www.cs.colostate.edu/helpdocs/vi.html for a tutorial on how to use
vi. You will find many such tutorials on the internet.
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emacs Starts the emacs editor. This is a much more powerful editor. This link gives you an idea of its
capabilities and provides a tutorial introduction: http://www.gnu.org/software/emacs/tour/
chmod [options]
Changes the read, write and execute permissions on your files. The default is that only you can
look at them and change them, but you may sometimes want to change these permissions. For
example, “chmod o+r ” will make the file readable for everyone, and
“chmod o-r ” will make it unreadable for others again. Note that for
user1 to be able to read a file created by user2, all containing directories for that file need to be
at least executable for user1.
tar Used to create file archives and extract files from a supplied archive. This is a sort of equivalent
for winzip, without actual compression. For example, “tar -xvf filename.tar”
‘untars’ the tarball or tar archive contained in filename.tar, including the hierarchical directory
structure. The command “tar -xvf filename.tar -C ~user1/test”
will extract to the specific directory ‘~user1/test’. The command “tar -cvf dirname”
will generate an archive consisting of all contents of folder dirname to “dirname.tar”.
gzip Compresses files. “gzip” produces files with the ending '.gz' appended to the original
filename. For example, “gzip tarball.tar” will produce the file ‘tarball.tar.gz’.
gunzip
Uncompresses files compressed by “gzip”.
grep
A very useful and powerful utility that searches for the text pattern ‘string’ in filenames.
For example, “grep ‘foo’ filename1 filename2” looks for the pattern
‘foo’ in filename1 and filename2. “grep” uses regular expressions for specifying
patterns. You can look up regular expressions for example on the internet here:
http://www.regular-expressions.info/quickstart.html.
top Provides an ongoing look at processor activity in real time, displaying a listing of the most CPU-
intensive tasks on the system. It provides an interactive interface for manipulating processes. For
example, if your username is user1, typing “top”, followed by “u” (which prompts you for a
username), and “user1” will list your processes. You can also terminate processes
interactively by typing “k” when running “top”, when you will be prompted for a PID. You
will also be prompted for a ‘kill’ option such as ‘9’.
ps -u Lists all the processes started by . The listing contains lots of information including the
process ID or PID, which is very useful if something crashes and you need to kill processes
individually, as well as the total time a process has been running etc.
kill [options]
Kills (terminates) the process having the process identifier (a number). This works only
for your own processes. You can get the PID by using “ps”. “kill” used on its own without
an optional attempt to terminate the process gracefully, giving it a chance to finish important
business such as flush buffers etc. If the process does not terminate (give it some time!), use the
option -9 or -KILL as in “kill -9 ” or “kill -KILL ”.
You should generally kill off ‘ghost’ processes that are artefacts of crashes or are otherwise not
performing any useful function. For example, Cadence starts many processes with a leading ‘cds’
in the name, such as “cdsMsgServer”, “cdsServIpc”, “cdsNameServer” etc. Another common
process is “obNameServer”. Sometimes Cadence crashes, when these processes remain running
in the background. You should locate these processes using “ps -yourUserName” or
“top” (see below) and kill them before restarting Cadence.
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Note:
• A very useful utility in Unix is command completion. If you type the partial name of a command
or a file name and press the tab, Unix will complete the command or file name, and prompt you
if there is no unambiguous choice. This helps when typing long commands. For example, rather
than typing “gunzip”, typing “gun” followed by the key will complete the command.
• Typing “gu” and pressing “tab” will not produce a completion in the first instance because
several other available commands begin with “gu” (eg: “guile” and “guile-tools”.
However, if you press the “tab” key a second time, all the commands will be listed, so this is
also a neat way of checking what commands or files are available.
• Also, the up arrow will cycle through previous commands.
1.5 Acknowledgements
These labs have been compiled from a combination of knowledge and information gained by personal
experience of using this tool at various institutes, teaching documents available via the internet or acquired
through personal contacts, and Cadence documentation. References are cited wherever text or diagrams are
taken from another source. The following websites have been particularly useful:
1. https://www.mics.ece.vt.edu/ICDesign/Tutorials/Overview/index.html [Retrieved Jan. 2023]
2. https://inst.eecs.berkeley.edu/~cs250/fa10/ [Retrieved Jan. 2023]
2 Introduction to Cadence
2.1 Configuring Your Unix Environment for Cadence
When you log in, you always start out in your 'home directory', which is the directory allocated to you as a
user. For example, if your login name is user1, you will be in the directory “/home/user1/linux”.
You have written permission only in your home directory. You can always return to your home directory
by typing “cd” without arguments.
It is necessary to create a directory from where you always start Cadence since a lot of files and
subdirectories are automatically generated. This way, you can keep the environment for this Unit separate
from the environment for other Units.
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Note:
• You must follow the naming convention outlined in each lab very precisely. These names will be
assumed by the automated test bench scripts that will check your submitted designs.
• Some characters are not interpreted literally in UNIX. For example, the ~, !, $, *, ?, \ , / and blank
spaces are called meta-characters and can cause problems when used in file names, because they
have other purposes in UNIX and are interpreted as instructions. Thus, you should avoid any
name with the above characters (such as a cell named “nand3 new” or a library named
“lab/2019”), since it may cause strange errors in the later stages of the design phase.
• Designs in Cadence are called cells. Cells that logically belong together are organised into a
library. You should have a single library called “lab2024” where you save all your cells. The
naming convention you should follow is shown in Table 2. These names will be repeated at the
point of creating the cell in each lab assignment. You should see “lab2024” instead of
“lab2018” mentioned in some of the Figures.
TABLE 2. Library and cell naming convention for Lab Coursework
Library
Name Cell Name Lab No. Description
lab2024 inv 1 Inverter cell
tb_inv 1 Testbench for the inverter
nand3 2 3-input NAND gate
tb_nand3 2 Testbench for the nand3 gate
invParam 3 Parameterised Inverter Cell
tb_invParam 3 Testbench for the Param. Inverter
Task 2.1: Setting Unix Environment for Full-Custom Design
(Laboratory Usage)
1. Once logged on, select Applications --> System Tools -- > Terminal.
2. Once the terminal window is open, type “cd”, which ensures you are in your home directory.
3. Type “module use /eda/cadence/modules”.
4. Type “module load course/EENG_3M_4050” to create a new working directory for Cadence.
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5. Type “vlsi_setup” to setup the VLSI directory (~/VLSI) and type “cd VLSI” to enter it . On future
runs, you can type “cd EDA/VLSI” to enter the VLSI directory that is already set up.
6. Start Cadence by typing: “ams_cds &”.
(Remote Access)
Note: It is strongly suggested to access the software in the lab only. If you need to remote access the
software and you face any issues, you should directly contact IT services for support.
1. For remote Linux desktops follow the instructions in this link based on your operating system:
https://uob.sharepoint.com/sites/itservices/SitePages/fits-engineering-linux-x2go.aspx
2. Once logged on to x2goclient, select Applications --> Terminal Emulator.
3. Once the terminal window is open, type “cd”, which ensures you are in your home directory.
4. Type “module use /eda/cadence/modules”.
5. Type “module load course/EENG_3M_4050” to create a new working directory for Cadence.
6. Type “vlsi_setup” to setup the VLSI directory (~/VLSI) and enter it. On future runs, you can type
“cd EDA/VLSI” to enter the VLSI directory that is already set up.
7. Start Cadence by typing: “ams_cds &”.
Note:
• The ampersand character (&) at the end of the command is to have the Cadence executable run in
the background, which frees up the xterm to accept other commands. This is a general Unix
utility and works with any command. You can leave a space between the final argument and the
ampersand as shown or have no space.
When you run this script for the first time, several configuration files are created. In the xterm you will see
various messages.
All messages beginning with “Creating..” relate to initialisation files that are created the first time
you run the tool, and will not appear again. The last line tells you that the Cadence executable virtuoso
is running, with the Hit-Kit version 4.10, (which is the technology kit supplied by AMS and relates to
libraries and process-related information), with a C35B4 technology that refers to a 0.35 m 4 metal
CMOS technology.
You should now have the following windows open:
- The Select Process Option window, which lists the available options for the C35B4 process. YOU
MUST SELECT “C35B4C3 PIP VG5 HIRES”, then press “OK” (see Figure 1 ).
- The Command-Interpreter-Window or CIW for short (Figure 2) is the main Cadence window
which echoes the main log created as “~/cds.log”. This window prints diagnostic
and error messages from the various other tools that Cadence starts up. Closing the CIW will cause
Cadence to exit.
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- The Library Manager, which lists all available libraries, and provides a menu-driven GUI for
performing common tasks such as creating/copying/deleting libraries and cell views (Figure 3 ).
If for any reason the Select Process Option window is not visible, go to the CIW menu bar, select Hit-Kit,
and then select Process Option from the drop-down menu. A Select Process Option window will pop up
(Figure 1). Select the “C35B4C3 PIP VG5 HIRES” option and click “OK”.
FIGURE 1. Fabrication process options
FIGURE 2. The CIW
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FIGURE 3. The Library Manager
At this point, you should have two windows open, the CIW and the Library Manager. You should now
have a look at the contents of your Cadence working directory, by typing “ls” into the Linux terminal
window, which will list the files present. Two important files are the “cds.lib” and the “.cdsinit”
file. Type “ls -al” if you don’t see these files.
The “cds.lib” file is the library definition file, which tells Cadence where the various supplied and user-
defined libraries are available.
The “.cdsinit” file specifies user customisation of the general tool environment.
Additionally, various other configuration files specify the configuration for various other tools that will be
used later, such as the layout editor.
2.2 Using the Cadence Documentation
At any time, you can type “cdnshelp&” into the terminal to launch the Cadence document server. You
can do a text search or access the various user guides separately. This is a valuable source of information,
and many manuals, tutorials and user guides exist for various parts of the tool. The Cadence help should be
your first source of reference whenever you have a query.
2.3 Cadence Design Flow
In the full custom design, the basic flow is to create the schematic according to the specifications, and then
the layout according to the schematic (see Figure 4).
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Creating a schematic to match the specifications is the more straightforward of the steps, due to the higher
level of abstraction. Creating a layout to match the schematic is much more difficult, as it consists of
manipulating polygons of different materials on several layers, and even creating a wire (metal connection)
between two nodes is a complicated task in comparison with schematic entry.
In layout design, a primary check that needs to be carried out is called a Design Rule Check or DRC for
short. This is a check that the layout does not violate any of the design rules for the targeted technology,
such as spacing rules. This is an automated check that is specified by rule files, which were set up when
you ran the “ams_cds” script for the first time.
A second check is that the layout matches the schematic, through a Layout vs Schematic or LVS check. This
is an automated tool task in Cadence.
A final check is to extract the parasitic resistances and capacitances from the layout, the unintended artefacts
of the layout, and simulate the schematic with these parasitics in place so that wires are not treated as
equipotential regions but rather as resistive-capacitive (RC) lines, and capacitive coupling between nodes
is accounted for.
It almost always happens that when running these checks, errors are discovered, or the circuit does not
match the required specifications, and the layout needs to be modified. The number of these iterations can
be high depending on the complexity of the circuit, and typically we move back and forth between the
circuit schematic and layout.
Various tools handle the flow between the schematic, layout, and simulation. Each lab in the coming weeks
will examine these steps in detail. In the rest of this lab, you will create an inverter schematic and run a first
analogue simulation.
FIGURE 4. The waterfall design flow
2.4 Running Cadence in Subsequent Lab Sessions
(Laboratory Usage)
In the first instance of running Cadence, it was necessary to stipulate the AMS C35B4C3 process, which
initialised the creation of the associated files within your Cadence working directory. This process is not
necessary again, thus in all future lab sessions, Cadence should be run as follows.
1. Once logged on, select Applications --> System Tools -- > Terminal.
2. Once the terminal window is open, type “cd”, which ensures you are in your home directory.
3. Move into your (/VLSI) Cadence working directory, by typing “cd EDA/VLSI”.
4. Type “module use /eda/cadence/modules”.
Schematic
Layout
Specifications
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5. Type “module load course/EENG_3M_4050” to create a new working directory for Cadence.
6. Start Cadence by typing: “ams_cds &”.
(Remote Access)
1. Once logged on, select Applications --> Terminal Emulator.
2. Once the terminal window is open, type “cd”, which ensures you are in your home directory.
3. Move into your (/VLSI) Cadence working directory, by typing “cd EDA/VLSI”.
4. Type “module use /eda/cadence/modules”.
5. Type “module load course/EENG_3M_4050” to create a new working directory for Cadence.
6. Start Cadence by typing: “ams_cds &”.
3 Schematic Entry
3.1 Creating a New Library
The first task is creating a new library where your new schematics will reside. The Library Manager
(Figure 3) is a design management tool that helps us navigate the different libraries and cell views, including
the supplied libraries as well as the project libraries.
You will see that under the “Library” tab, many libraries are already defined. Two libraries that we will
be using very often are “analogLib”, a Cadence-supplied library for common components such as
ground, vdd and voltage and current sources, and “PRIMLIB”, an AMS-supplied library that contains
parameterised transistor cells among other components that we can use directly. We will see how to use
these libraries later. The first task is to create a new library where you will be storing the different views of
the inverter.
Task 3.1: Create a New Library
In the Library Manager, choose File → New → Library. Enter “lab2024” (note without spaces) for
the library name and click “OK”.
You will now get a question about a technology file to be attached to this library, see Figure 5.
Click “Attach to an existing technology library”, then select “TECH_C35B4”, as in
Figure 6. You should now see the new library lab2024 in the Library Manager, as well as a confirmation
message in the CIW.
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FIGURE 5. Attach to an existing technology library
FIGURE 6. Attach to the C35B4 technology
3.2 Designing an Inverter
In addition to lecture notes, you can refer to Chapter 5 of Rabaey1 for details related to the design of the
CMOS inverter and Chapter 6 for general considerations on the complementary design style and transistor
sizing. Chapter 2, Section 2.5 of Weste2 also covers inverter design considerations.
The inverter schematic is given in Figure 7 (body terminals are also shown). The minimum gate length
(L) of a MOSFET in the AMS 0.35 m Hit-Kit process is 0.35m, while the minimum width (W) is 1m,
due to process design rules. Hence a minimum-sized transistor has a W/L ratio of 1m/0.35m.
1Jan M. Rabaey et. al., Digital Integrated Circuits, A Design Perspective, 2nd International Edition,
Prentice Hall, Pearson Education International, ISBN:0-13-120764-4.
2Neil H. E. Weste and David Money Harris, CMOS VLSI Design, 4th ed. ISBN: 0-321-54774-8
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FIGURE 7. Inverter schematic
Note:
• This is not a ratio that is meant to be computed as a decimal number. The numerator in the
W/L ratio gives the width, and the denominator the length of the transistor. Simplifying it
into a decimal number removes important information. For example, W/L=2m/1m and
W/L=4m/2m both result in the same ratio, and hence the same electrical drive strength or
effective on resistance, but are two very different transistors, with different parasitic
capacitances.
• Hence the size of a transistor should always be presented as a fraction, as above, with
dimensional units.
The difference in electron and hole mobility in the Hit-Kit process is roughly a factor of 2. Hence a
minimum-sized inverter with the symmetrical rise and fall waveforms needs to have a PMOS of
2m/0.35m and an NMOS of 1m/0.35m (Figure 7) if required. Some designs may have minimum-
sized transistors in both the pull-up (PMOS) and pull-down (NMOS) networks.
Task 3.2: Adding a Cell to the Library
In the Library Manager window, select the “lab2024” library and choose File → New → Cell View.
The “Cell Name” is “inv”, while the “View Name” is schematic and ensure that under
“Application”, it is set to “Schematic L” (Figure 8). Click “OK”.
Note:
• You may get a message about not being able to obtain a license for this tool, asking permission to
obtain a higher-tiered license. You should select “Always” for these messages, then click “OK”.
1m m
in o
m m
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You are now presented with the Virtuoso Schematic Editor L schematic entry tool for the cell you just
created. If you check in the Library Manager, you will see that a cell called “inv” with view name
“schematic” has been added to the “lab2024” library.
In the Virtuoso tool add the PMOS and NMOS transistors that comprise the inverter by choosing Create
→ Instance... i and a dialogue box will open. Type “PRIMLIB” in the library and either type in “nmos4”
and “symbol” for the “Cell” and “View” fields respectively or use the browse button when another
dialogue box will open, and you can select this particular component. If you select to browse ticking “Show
Categories” can be helpful. Select PRIMLIB --> Mosfets --> LV --> NMOS4/PMOS4. After
selecting it, click close and you will be returned to the initial dialogue box of Figure 9.
You will see that default values are filled in for various fields. Since we want a minimum-sized NMOS, the
width must be changed to “1u”. Change the value in the “Width” field to “1u” and press the “tab” key.
You will see that the “Width Stripe” value also changes to “1u”. Scroll down and have a look at all
the fields; leave them unchanged. Click the “Hide” button at the bottom.
FIGURE 8. Adding a schematic view for the inverter cell
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FIGURE 9. Adding a component in the schematic editor
If you now move the mouse to the schematic window, you will see a yellow transistor symbol moving with
the mouse pointer. You can click anywhere to place instances of this component. To stop placing instances
of the “nmos4” component, press the “Esc” key.
To place the PMOS transistor, repeat the above procedure except that the cell is now “pmos4”, and the
“Width” and “Width Stripe” have to be “2u”.
Note:
• The “Width Stripe” is relevant when designing very large transistors, as the gate can be
implemented in multiple fingers rather than a single long strip of polysilicon.
• If a letter appears at the end of any menu command, you can type that letter as a shortcut for the
command. For example, pressing “i” with the schematic window selected will bring up the same
dialogue box.
• If three dots appear immediately after a command in the menu (as in command...), it is an
indication that selecting that command will result in a dialogue box opening. Some commands
just activate a specific mode in the selected tool window. For example, Create → Wire (narrow)
w does not open a dialogue box but enables a narrow wire drawing mode in the schematic
window.
• If you want to change the value of any field after placing a component, simply select the
component and choose: Edit → Properties → Objects... Q or simply select the component
and type “q” (lower case, i.e., without if you are typing the letter).
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Add two more components “vdd” and “gnd” from the library “analogLib”. Place the transistors, vdd
and gnd approximately as shown in Figure 10.
Note:
• You can move objects around by selecting Edit → Move M and pointing at the new placement.
Alternatively, you can click on any component to first select it, when a white boundary box
around the object will show the selection. Next, move the cursor over the selection so that it
becomes a four-directional arrow shape and drag it anywhere using the left mouse button.
• You can escape any mode in the schematic editor window by pressing the “Esc” key.
• You will find a short explanatory message in the bottom left corner of the schematic window for
most commands, describing the next step in that particular command.
Now you should add the wires to connect the schematic as shown in Figure 7. You can either use the
command Create→ Wire (narrow) w, use the keyboard shortcut “w”, or press the appropriate button on
the toolbar at the top of the schematic window. Pointing the cursor at any of these buttons will cause an
explanatory message to pop up. You could also simply “drag” any of the connection nodes onto any other
node without using the explicit command, and a narrow wire will be drawn. Make sure to connect the body
terminals.
Now the input and output pins should be added. Point the cursor at the buttons on the bottom menu on top
until you see the pop-up message “Create Pin” and click it. Or simply press “p”. The Add Pin form of
Figure 11 should appear. Type “in” as shown in the “Pin Names” field in Figure 11. Since “in” is an
input pin, the rest of the field settings are correct. Move the mouse over the schematic window and click
once to place the “in” pin approximately as in Figure 10.
Select the Add Pin dialogue box again and add another pin, this time type “out” into the “Pin Names”
field and change the direction to “output”. Place this output pin as well. Connect the pins according to
the schematic and you should now have a schematic similar to that of Figure 10.
Choose File → Check and Save Shift+X, and make sure there are no errors.
Note:
• A useful command in the schematic editor is the fit command available from View → Fit for
simply the key “f”. This will zoom the contents in the schematic window so that everything is
shown. You can also zoom out with the “[” key and zoom in with the “]” key. Finally, selecting
an area by right-clicking and dragging the cursor to create a rectangle will zoom to the area
covered by the rectangle.
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FIGURE 10. The inverter schematic in the schematic editor
FIGURE 11. Adding pins in the schematic editor
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3.3 Creating a Symbol for the Inverter Schematic
In general, you would want to design a gate once and then re-use it wherever you need to. A primitive way
of doing that would be to cut and paste the schematic. A better way is to create a symbol for the gate and
place that symbol wherever you want to use the gate. This is an example of a hierarchical design style.
Whenever you use an instance of a cell, you should use the symbol view where available. In Cadence, it is
relatively straightforward to create a symbol for custom schematics.
Note:
• Ideally you would want to be able to change critical parameters in a cell when you re-use it, such
as the transistor sizes. This is possible by creating parameterized cells. You will learn how to do
this in the next lab.
Task 3.3: Creating an Inverter Symbol
In the schematic window, choose Create → Cellview → From Cellview... and a dialogue box will open
up. Keep the default settings and click “OK”. A second dialogue box specifying the settings for symbol
generation will appear. Ensure that “in” and “out” are entered in the “Left Pins” and “Right Pins”
fields, respectively, and click “OK”. The Symbol Editor will open.
Note:
• In a symbol, the green lines and text boxes are visible when you place the symbol in a schematic.
The red rectangle is not visible; instead, it demarcates the footprint of the symbol when selected.
You can resize anything and delete and add any shape you want. Many shapes such as lines, arcs, rectangles,
polygons etc. are available under Create → Shape →. Delete the green rectangle, resize the red rectangle,
and create a shape that is more reminiscent of an inverter, such as shown in Figure 12. Make sure to do a
File → Check and Save and then close the Symbol Editor. If you now have a look in the Library
Manager, you will find that the “inv” cell includes a symbol view.
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FIGURE 12. The inverter symbol in the symbol editor
3.4 Creating a Test Bench
To check the functionality of the circuit we just designed, some sort of test bed with input stimulus is
necessary. It would be possible to add this to the inverter schematic, but this would be poor practice for
several reasons. Firstly, the separation of the component’s development and testing allows the modularity
of the component to be preserved, so that the component description is not confused with circuitry related
to its testing.
Secondly, it enforces more robust testing by the similarity with the component’s real-world usage scenario,
where it would typically be placed in a larger system. This makes comparisons against specifications easier.
It also allows separate teams to oversee testing and development, an important strategy when designing
large and complex systems.
Thirdly, any unwanted changes in the functionality because of changes to the internal implementation of a
component or block in repeated iterations can be traced. So, for example, a component that has been revised
to operate faster can be tested using the same test bench, and any changes in the functionality can be more
easily identified.
Task 3.4: Create a Testbench Schematic
In the Library Manager window, select the “lab2024” library and create a new schematic by choosing
File → New → Cell View. It is good practice to name all testbenches with a leading “tb” (or something
equally descriptive). In the tutorial, the name used is “tb_inv”.
Add an instance of the symbol view of the inverter that you created by pressing “i” in the schematic editor
window and entering “lab”, “inv” and “symbol” for the “Library”, “Cell” and “View” fields
respectively in the Add Instance form.
From “analogLib”, add instances of “gnd” and “vdd”, as well as “cap”, “vpulse” and “vdc”,
accepting the default values in the Add Instance form for now. We will change them soon to match the
required stimulus.
Arrange the components and wire them up as shown in Figure 13. Note that the input to the inverter is the
“vpulse” component, and the “vdc” component is just connected between “gnd” and “vdd”, forming a
separate circuit. Also, note that two instances of the “gnd” cell (component) are necessary. You can either
insert it twice or copy the first using the “c” command.
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Now we need to change the values of some of the components we added. Select the capacitor and press “q”
to display its properties. Change the capacitance from the default of 1p to 12f (i.e., from 110−12 to 1210−15)
F. Display the properties of the “vpulse” component, and change the values of “Voltage2”, “Delay
time”, “Rise time”, “Fall time”, “Pulse width” and “Period” as shown in Figure 14. In the
“vdc” component, change the DC voltage value to 3.3.
Note:
• Take a moment to understand the test bench structure. The circuit on the left-hand side is a simple
way to specify the value of vdd. The reason you chose 3.3V is due to the specified rail voltage
for the transistors in the Hit-Kit process. The circuit on the right-hand side consists of the inverter
with input stimulus and load.
• The inverter schematic had two pins, “in” and “out” to which the input stimulus and load are
connected. The schematic also had power and ground rails connected to “vdd” and “gnd” cells.
Because exactly the same cell symbols, and consequently net names, are used in the testbench
and schematic, a short is assumed between the “vdd” in the test bench schematic and the “vdd”
in the inverter schematic. The same applies to “gnd”. As a general rule, if two nets share the
same name, they are assumed to be shorted.
• Hierarchically designed circuits can be traversed by using the
Edit → Hierarchy → Descend Edit... Shift+E command or the
Edit → Hierarchy → Descend Read... E command.
Select the inverter symbol, press “e” and select schematic in the ensuing form to see the
schematic you created in read-only mode. Press “ctrl e” to return. The Descend Edit
command is useful if you wish to change something simple in the schematic, such as the width
of a transistor.
FIGURE 13. The inverter test bench
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FIGURE 14. Properties of the vpulse component in the inverter testbench
3.5 Running a Simulation
This section describes how to run a first transient simulation, and how to look at input and output
waveforms. The Cadence simulator is called Spectre.
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Note:
• In addition to transient simulations, many kinds of simulations can be run, including DC (“dc”),
small signal (“ac”), pole-zero (“pz”), transfer function (xf), noise (“noise”) and s-parameter
(“sp”), where the terms in the parenthesis denote the Spectre name for the analysis. Most of the
traditional small signal analyses that depend on a dc operating point (ac, xf, noise etc.) are also
available in the periodic form, with a leading “p” in the name, such as “pac”, “pxf” and
“pnoise”. The next lab describes common simulation-related issues and tasks in a little more
detail, but you should refer to the Spectre user guide available from “cdnshelp” for
comprehensive documentation.
Task 3.5: Running a Transient Simulation
All simulations are carried out by choosing Launch → ADE L from the schematic window. This opens the
Analog Design Environment tool shown in Figure 15.
Situated on the right-hand side are some short-cut buttons. Point the cursor to each of these buttons and
click on the one that says, “Choose Analyses...”. Tick the “tran” button and enter 10n in the
“Stop Time” field. Also, ensure that the “Enabled” button is ticked as in Figure 16 and click “OK”.
In the Analog Design Environment window, select Outputs → To Be Plotted → Select On Design. The
schematic window will automatically become current. Select the input and output nets (blue wires) by
clicking on them one after the other.
Note:
• If you want to save and plot the currents, you have to click on the relevant node of a component,
not the wire itself. By default, Cadence does not save the currents.
In the Analog Design Environment window, run the “Netlist and Run” command by clicking on
the green play button. You may get a Welcome to Spectre notice to which you can click “OK” straight
away. If you followed all the instructions correctly, the simulation should run properly and both a textual
output window as well as a waveform output window as shown in Figure 17 should open. Identify the input
and output waveforms.
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Note:
• This is a powerful waveform viewer with many useful features. Just as in the schematic window
right-clicking and selecting an area will zoom to that area. Pressing “f” will restore the full
waveform. Point the cursor to the buttons on the top and press the one that corresponds to
“Split All Strips”. All waveforms will be plotted separately. Clicking the “Combine
all Analog Traces” button will re-plot all waveforms in a single set of axes. The menu
command Marker -> Create Marker allows you to set various types of markers for
measurements.
FIGURE 15. The Analog Design Environment simulation tool
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FIGURE 16. Transient analysis settings in the Analog Design Environment
FIGURE 17. Input and output waveforms for the transient analysis
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Task 3.6 Observing the Effect of Transistor Sizing
In the schematic window, select the inverter symbol and press “E” to descend the hierarchy and edit the
original schematic. Change the width of the PMOS to “6u” and the width of the NMOS to “10u”. Check
and save the schematic and return to the original circuit by pressing “ctrl e”. Check and save again.
Simulate the test bench again by pressing the green traffic light button in either the ADE window or the
Virtuoso Analog Design Environment L Editing (schematic editor) window. The output waveform in the
Virtuoso Visualization & Analysis XL window will be automatically updated. Observe the differences in
the falling and rising waveforms of the output.
What you need to upload to Blackboard:
Upload all answers to Exercises 3.1 and 3.2 including workings to Blackboard as a single PDF named
“lab1.pdf”. Have two headers Exercise 3.1 and Exercise 3.2 and use the same numbering as here. Please
do NOT upload multiple files. Remember, these exercises are meant to be attempted individually with no
discussion with either classmates, lecturer or lab demonstrators.
Exercise 3.1: Calculate the Equivalent Resistance of Minimum-sized Transistors
1. From simulations extract the delay values from the 50% point of the input waveform to the 50%
point of the output waveform for both low-to-high (tpd_LH) and high-to-low (tpd_HL) transitions at the
output and fill in the following table (remember to include correct units). Remember to add a screenshot
of the input and output curves with a horizontal marker at 1.65 V (as described in the next Note section)
and label low-to-high and high-to-low delays. For these simulations, the W/L ratios for PMOS and
NMOS FETs should be 2m/0.35m and 1m/0.35m respectively, while the load capacitance
should be 12 fF. (7/100)
Input Output tpd_LH tpd_HL
low-high high-low N/A
high-low low-high N/A
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Note:
• To check the delay at a given threshold, select the waveform window (called Virtuoso
Visualization and Analysis XL) and type “h”. A horizontal marker will be placed in the window
at some point based on where your cursor is currently. If you point the cursor at the marker, the
cursor will change to an up-down arrow, which will allow you to drag the marker up and down.
When your cursor is pointed at the marker, you can also right-click to open a dialogue box
showing the marker’s properties. Right-click and select the first menu item “Horizontal
Marker Properties”. This will open a new dialogue box that will allow you to set the “Y
Position”. Change the value here to 1.65V, which is the mid-point between the ground and
the power rail. Click “OK”. The marker will move to the mid-point between rails and the plot
will be populated with callouts showing the time values at the intersection between the marker
and the input and output waveforms.
• Right-click and select the relevant portion of the graph to zoom in.
2. For this and the following exercises you should use the switch/resistor model of the FET
introduced in Lecture 2. Sketch the equivalent circuit for the output capacitance being charged from
0 to Vdd comprising a voltage source, the equivalent ON resistance of the PMOS transistor Rp and load
capacitor CL (12 fF). (5/100)
3. Write down the expression for the voltage across the load capacitor VOUT in terms of Vdd, Rp and CL as a
function of time, t. Then derive the 50% delay equation to calculate the value of Rp based on the delay
you observed in the Exercise 3.1, section 2 simulation. (6/100)
4. Knowing the Rp value from Exercise 3.1, section 4, what is the equivalent resistance Rp,min of a
minimum-sized PMOS transistor (i.e., W/L= 1m/0.35m) (Analytical calculation)? Now, run the
inverter simulation with a minimum-sized PMOS transistor, and calculate Rp,min based on the simulation
result and compare it with the analytical calculation value. (6/100)
5. Using the same method in Exercise 3.1, section 4, considering the W/L ratio for the PMOS FET is
1m/0.35m, calculate the value of Rn,min, the equivalent ON resistance of a minimum-sized NMOS
transistor. (6/100)
Exercise 3.2: Calculating the Effect of Transistor Sizing
1. It is required that your inverter drive a load of 25 fF with a maximum 50% delay of 100 ps for both
rising and falling edges. Using the resistor model of the transistor (i.e., the resistance is inversely
proportional to the W/L ratio), calculate the required W/L ratios and the widths assuming a minimum
length, of the PMOS and NMOS transistors to achieve this delay (Analytical calculation). You can use
Rp,min and Rn,min values from simulation results in sections 5 and 6 in Exercise 3.1. (10/100)
2. Simulate the inverter with the NMOS and PMOS transistors analytically calculated new W/L ratios in
Exercise 3.2, section 1. Comment on any deviations of the simulated delay values compared to
calculations. Remember to add the screenshot of input and output waveforms and label low-to-high and
high-to-low delays. How can the accuracy of the switch model be improved? Sketch the new equivalent
switch/resistor model circuit that would result from this improvement. (10/100)
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Confidentiality of AMS Hit-Kit
I agree not to disseminate, divulge, or reveal to anybody, any AMS process or design library related
information made available to me by the University of Bristol, and will only use them to complete tasks
and exercises prescribed in the EENG 34050/ EENG M4050 unit.
Confidential material includes AMS-supplied models, library files, datasheets, documentation and
simulation results based on AMS device models or standard cells that allow comparisons to be made against
other processes.
Name (PRINT): __________________________________________________________________
Signature: __________________________________________ Date: ______________________