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时间：2024-03-09
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 1/12
COMP2300/6300/ENGN2219 / Assessments / Checkpoint 1: Digital Logic
Checkpoint 1: Digital Logic
Complete summative tasks in Digital
A Digital Circuit
On this page
Outline
Rules and Policies
Allowed Components
Specication
Exercise 1 - Demux Negator (1 Mark)
Exercise 2 - ALU Extended (1.5 Marks)
Exercise 3 - 2 Register Counter (1.5 Marks)
Marking Criteria
Submission
Getting Started
Completion Checklist
Gitlab CI and Artifacts
PDF Artifact
FAQ
My circuits don’t work, can I email you for help?
It’s [5 minutes, 60 minutes, 12 hours] before the deadline and my CI Jobs aren’t nishing!
How do I know my assessment has been submitted?
In this assessment you are going to complete a number of Digital les to a required spec,
much like what you have already been doing in the labs.
To complete this assessment you should have completed the week 1, week 2 and week 3
labs as well as watched the week 1, week 2 and week 3 lectures.
Outline
Deadline: 15 March 2024, 11:59 pm
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 2/12
Assessment template: link
Specication: keep reading
Weighting: 5%
Marked out of: _ / 5
Time Until Deadline (15 March 2024, 11:59 pm):
6:06:42:20
Rules and Policies
this is an individual assessment task, ensure you fork your repo as private
you may re-use designs / les from your labs
it is your responsibility to ensure any additional les are included in the repo
and pushed to gitlab correctly
your main solution still needs to be in the provided les
all submitted les should abide by the style guidelines
late submission is not permitted without an extension
Allowed Components
You may use any component digital provides you, with the following exceptions:
Lookup Table
Counter
Counter with preset
Negation (Components > Arithmetic > Negation)
VHDL / Verilog / Anything outside of Digital
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 3/12
Submissions that use any of the above will have marks deducted accordingly.
Specication
Exercise 1 - Demux Negator (1 Mark)
For the rst exercise, your goal is to design a circuit that:
Takes in a 2-bit input A and has two 2-bit outputs, Q and U
Sends A to one of the two outputs based on a 1-bit selector ( S )
Sends a default value given by the input DEF to the other output
Conditionally negates (inverses) the 2-bit input A based on a 1-bit input ( T )
This leaves us with the following output table:
A DEF S T Q U
a b 0b0 0b0 a b
a b 0b1 0b0 b a
a b 0b0 0b1 ~a b
a b 0b1 0b1 b ~a
Where a and b are some 2 bit binary value, and ~a and ~b are their logical negation
(inverse).
Eg: a = 0b1011 , ~a = 0b0100 .
You are required to rst complete a 1-bit demultiplexer with default value in the le
ex1_demux.dig , and then use this in your circuit to extend it to 2-bit inputs and allow
conditional negation.
Complete the ex1_demux and ex1.dig les according to the above specication.
Exercise 2 - ALU Extended (1.5 Marks)
In this exercise, you will extend the ALU you created in lab 2.
Your task is to design a circuit that:
Takes in 2, 16-bit inputs ( A , B )
Performs the appropriate operation on the inputs based on a 3-bit selector ( ALUOP )
Outputs the 16-bit result ( RESULT )
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 4/12
Sets ags as necessary ( FLAG )
Here is the table for the ALUOP selector:
ALUOP Operation
0b000 ADD
0b001 SUB
0b010 AND
0b011 XOR
0b100 NAND
0b101 XNOR
0b110 OR
0b111 NOR
For a description of how to set the ags, please refer to the lab 2 page.
A quick summary:
Z ero: set if the result is all 0 s
N egative: set if the result is negative for 16-bit two’s complement (most signicant bit
is 1 )
C arry: set if the addition of 2 inputs is larger than what can be represented in 16 bits
0 for non-arithmetic operations (carry not set)
o V erow: set if the sign bit (most signicant bit) of 2 inputs is the same, but the
result after an addition is different from the inputs’ sign bit
0 for non-arithmetic operations (overow not set)
For the above denitions, we consider subtraction to also be performed as an
addition, read here if you are confused as to why.
Complete ex2.dig to the above specication.
Exercise 3 - 2 Register Counter (1.5 Marks)
For the nal exercise, you will combine registers and a counter circuit to build a 2 register
counter.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 5/12
Your task is to design a circuit that:
Contains two 16-bit registers labeled R1 and R2
Responds to the rising-edge of a clock line ( CLK )
Performs arithmetic and register modication operations based on a 2-bit selector (
OP )
Maintains register state throughout
The table for the OP selector is as follows
OP Operation
0b00 R1 := R1 + R2
0b01 R2 := R1 + R2
0b10 R1 := R1 + 1
0b11 R2 := R2 + 1
You have been provided registers in the ex3.dig le already. You should not delete or
rename these registers. The registers are also set as measurement values, which is critical
to the tests working properly; make sure if you end up deleting them accidentally that you
set this option again. Where this option is located is described in Lab 4 Exercise 1.
For example, the following table shows how the registers change over time with the CLK
line and OP code:
CLK OP R1 R2
0 X 0 0
C 0b10 1 0
C 0b10 2 0
C 0b10 3 0
C 0b11 3 1
C 0b11 3 2
C 0b00 5 2
C 0b01 5 7
Notes:
X is the same as Digital tests where it doesn’t matter what value it is at this time.
C also behaves like it does in Digital tests, see here for more info.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 6/12
Complete ex3.dig to the above specication.
Marking Criteria
Your assessment will be evaluated on the following criteria:
Correctness of your implementations (4/5)
Good practice with Digital circuit layout (1/5)
Item 1 will be evaluated primarily through the results of your Digital tests and the CI.
Item 2 will be evaluated by visually inspecting your submissions for neatness, efciency
and logical layout. For more information on how to lay things out well in Digital, check the
style guide.
Submission
Submission is through GitLab, the most recently pushed commit of your fork of the
assessment template before the deadline is taken to be your assessment submission.
Getting Started
read this assessment page completely
fork and clone the assessment template
ensure you fork your project as private
do NOT change the name or path of the repo, or it may get missed by our
software
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 7/12
work on each task, testing, committing and pushing as you go
make a mistake or get stuck, then ask a good question on the course forum.
Completion Checklist
you have completed the circuits in the les provided and have not renamed or moved
them
you have checked that you haven’t used any of the components listed above
you have run your les local test(s) and they pass successfully
you have laid out your circuits using good practice
you have saved, committed and pushed your Digital les to gitlab
you have lled out, committed, and pushed your statement of originality
you have checked the gitlab ci tests and they are passing
you have checked the pdf artifact on gitlab to ensure it is correct
Gitlab CI and Artifacts
For this assignment, your repo will be partially marked automatically (a tutor will still sight
it) based on the tests on gitlab. This is the CI that you may have already been seeing in the
labs, however now it isn’t just for your benet, so it’s important that you understand and
check it.
The correctness of your implementations will be marked based on passing the tests for
each one of the exN.dig les as well as the ex1-demux.dig tests. These tests will be
similar to the ones that are already present in the les, so if your digital les are testing
okay locally, then they should also be passing in the CI. However, it is best to make sure
that this is the case by going to the gitlab website to make sure the CI is passing as you’d
expect.
To view the CI pipeline for your repo, click on the little icon to the right of your most recent
commit.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 8/12
Then you’ll be presented with a list of the jobs, you’ll want to make sure that the jobs are
passing once you’ve completed the corresponding task.
Filecheck stages ensure that the le exists and has been updated from the default. Test
stages run the submitted les against our tests to measure correctness.
PDF Artifact
Your repo will be packaged into a pdf for marking purposes. As such it is important that you
see what the result of the pdf job is and make sure the output makes sense.
It will:
take your name and uid from the statement-of-originality.md
take images from your exN.dig les
take test results similar to those in the exN.dig les
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 9/12
take references from the statement-of-originality.md
To view the pdf, rst click the ci icon on your most recent commit (as above), then click on
the pdf job.
Then, you’ll be taken to the job page, where you should see a “Job Artifacts” section, click
on the Browse button.
This will allow you to preview your pdf. Which should look something like this.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 10/12
There is more general info about gitlab ci here.
FAQ
My circuits don’t work, can I email you for help?
Sorry, you won’t get help over email or Teams. We provide a course forum which is the only
way we are able to help.
Forum posts related to your assessment submission must be “private” (as for any individual
assessment task).
It’s [5 minutes, 60 minutes, 12 hours] before the deadline and my CI
Jobs aren’t nishing!
Unfortunately on the day that an assessment is due, when many students are pushing
updates at once, the CI servers can’t keep up. You may not see your CI jobs nish before the
deadline. You will just have to manually check that your les have been submitted correctly
and that you are passing tests locally.
The best way to avoid this issue is to start early and nish early
If there’s any issues with your git repository after the deadline. Please let us know (after the
deadline) through a private forum post and there may be something we can do.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 11/12
How do I know my assessment has been submitted?
If:
the les in your fork of the assessment are correct (i.e., the les you intend to submit)
when checking on the gitlab website
the time is before the deadline
then your assessment has been submitted (well done!).
Please don’t ask us to “check”, we would be just doing exactly the same thing as the above
steps which you can do yourself.
Acknowledgement of Country
The Australian National University acknowledges, celebrates and pays our respects to the
Ngunnawal and Ngambri people of the Canberra region and to all First Nations Australians
on whose traditional lands we meet and work, and whose cultures are among the oldest
continuing cultures in human history.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 12/12
Contact ANU
Copyright
Disclaimer
Privacy
Freedom of Information
+61 2 6125 5111
The Australian National University, Canberra
TEQSA Provider ID: PRV12002 (Australian University)
CRICOS Provider Code: 00120C
ABN: 52 234 063 906
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 1/12
COMP2300/6300/ENGN2219 / Assessments / Checkpoint 1: Digital Logic
Checkpoint 1: Digital Logic
Complete summative tasks in Digital
A Digital Circuit
On this page
Outline
Rules and Policies
Allowed Components
Specication
Exercise 1 - Demux Negator (1 Mark)
Exercise 2 - ALU Extended (1.5 Marks)
Exercise 3 - 2 Register Counter (1.5 Marks)
Marking Criteria
Submission
Getting Started
Completion Checklist
Gitlab CI and Artifacts
PDF Artifact
FAQ
My circuits don’t work, can I email you for help?
It’s [5 minutes, 60 minutes, 12 hours] before the deadline and my CI Jobs aren’t nishing!
How do I know my assessment has been submitted?
In this assessment you are going to complete a number of Digital les to a required spec,
much like what you have already been doing in the labs.
To complete this assessment you should have completed the week 1, week 2 and week 3
labs as well as watched the week 1, week 2 and week 3 lectures.
Outline
Deadline: 15 March 2024, 11:59 pm
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 2/12
Assessment template: link
Specication: keep reading
Weighting: 5%
Marked out of: _ / 5
Time Until Deadline (15 March 2024, 11:59 pm):
6:06:42:20
Rules and Policies
this is an individual assessment task, ensure you fork your repo as private
you may re-use designs / les from your labs
it is your responsibility to ensure any additional les are included in the repo
and pushed to gitlab correctly
your main solution still needs to be in the provided les
all submitted les should abide by the style guidelines
late submission is not permitted without an extension
Allowed Components
You may use any component digital provides you, with the following exceptions:
Lookup Table
Counter
Counter with preset
Negation (Components > Arithmetic > Negation)
VHDL / Verilog / Anything outside of Digital
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 3/12
Submissions that use any of the above will have marks deducted accordingly.
Specication
Exercise 1 - Demux Negator (1 Mark)
For the rst exercise, your goal is to design a circuit that:
Takes in a 2-bit input A and has two 2-bit outputs, Q and U
Sends A to one of the two outputs based on a 1-bit selector ( S )
Sends a default value given by the input DEF to the other output
Conditionally negates (inverses) the 2-bit input A based on a 1-bit input ( T )
This leaves us with the following output table:
A DEF S T Q U
a b 0b0 0b0 a b
a b 0b1 0b0 b a
a b 0b0 0b1 ~a b
a b 0b1 0b1 b ~a
Where a and b are some 2 bit binary value, and ~a and ~b are their logical negation
(inverse).
Eg: a = 0b1011 , ~a = 0b0100 .
You are required to rst complete a 1-bit demultiplexer with default value in the le
ex1_demux.dig , and then use this in your circuit to extend it to 2-bit inputs and allow
conditional negation.
Complete the ex1_demux and ex1.dig les according to the above specication.
Exercise 2 - ALU Extended (1.5 Marks)
In this exercise, you will extend the ALU you created in lab 2.
Your task is to design a circuit that:
Takes in 2, 16-bit inputs ( A , B )
Performs the appropriate operation on the inputs based on a 3-bit selector ( ALUOP )
Outputs the 16-bit result ( RESULT )
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 4/12
Sets ags as necessary ( FLAG )
Here is the table for the ALUOP selector:
ALUOP Operation
0b000 ADD
0b001 SUB
0b010 AND
0b011 XOR
0b100 NAND
0b101 XNOR
0b110 OR
0b111 NOR
For a description of how to set the ags, please refer to the lab 2 page.
A quick summary:
Z ero: set if the result is all 0 s
N egative: set if the result is negative for 16-bit two’s complement (most signicant bit
is 1 )
C arry: set if the addition of 2 inputs is larger than what can be represented in 16 bits
0 for non-arithmetic operations (carry not set)
o V erow: set if the sign bit (most signicant bit) of 2 inputs is the same, but the
result after an addition is different from the inputs’ sign bit
0 for non-arithmetic operations (overow not set)
For the above denitions, we consider subtraction to also be performed as an
addition, read here if you are confused as to why.
Complete ex2.dig to the above specication.
Exercise 3 - 2 Register Counter (1.5 Marks)
For the nal exercise, you will combine registers and a counter circuit to build a 2 register
counter.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 5/12
Your task is to design a circuit that:
Contains two 16-bit registers labeled R1 and R2
Responds to the rising-edge of a clock line ( CLK )
Performs arithmetic and register modication operations based on a 2-bit selector (
OP )
Maintains register state throughout
The table for the OP selector is as follows
OP Operation
0b00 R1 := R1 + R2
0b01 R2 := R1 + R2
0b10 R1 := R1 + 1
0b11 R2 := R2 + 1
You have been provided registers in the ex3.dig le already. You should not delete or
rename these registers. The registers are also set as measurement values, which is critical
to the tests working properly; make sure if you end up deleting them accidentally that you
set this option again. Where this option is located is described in Lab 4 Exercise 1.
For example, the following table shows how the registers change over time with the CLK
line and OP code:
CLK OP R1 R2
0 X 0 0
C 0b10 1 0
C 0b10 2 0
C 0b10 3 0
C 0b11 3 1
C 0b11 3 2
C 0b00 5 2
C 0b01 5 7
Notes:
X is the same as Digital tests where it doesn’t matter what value it is at this time.
C also behaves like it does in Digital tests, see here for more info.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 6/12
Complete ex3.dig to the above specication.
Marking Criteria
Your assessment will be evaluated on the following criteria:
Correctness of your implementations (4/5)
Good practice with Digital circuit layout (1/5)
Item 1 will be evaluated primarily through the results of your Digital tests and the CI.
Item 2 will be evaluated by visually inspecting your submissions for neatness, efciency
and logical layout. For more information on how to lay things out well in Digital, check the
style guide.
Submission
Submission is through GitLab, the most recently pushed commit of your fork of the
assessment template before the deadline is taken to be your assessment submission.
Getting Started
read this assessment page completely
fork and clone the assessment template
ensure you fork your project as private
do NOT change the name or path of the repo, or it may get missed by our
software
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 7/12
work on each task, testing, committing and pushing as you go
make a mistake or get stuck, then ask a good question on the course forum.
Completion Checklist
you have completed the circuits in the les provided and have not renamed or moved
them
you have checked that you haven’t used any of the components listed above
you have run your les local test(s) and they pass successfully
you have laid out your circuits using good practice
you have saved, committed and pushed your Digital les to gitlab
you have lled out, committed, and pushed your statement of originality
you have checked the gitlab ci tests and they are passing
you have checked the pdf artifact on gitlab to ensure it is correct
Gitlab CI and Artifacts
For this assignment, your repo will be partially marked automatically (a tutor will still sight
it) based on the tests on gitlab. This is the CI that you may have already been seeing in the
labs, however now it isn’t just for your benet, so it’s important that you understand and
check it.
The correctness of your implementations will be marked based on passing the tests for
each one of the exN.dig les as well as the ex1-demux.dig tests. These tests will be
similar to the ones that are already present in the les, so if your digital les are testing
okay locally, then they should also be passing in the CI. However, it is best to make sure
that this is the case by going to the gitlab website to make sure the CI is passing as you’d
expect.
To view the CI pipeline for your repo, click on the little icon to the right of your most recent
commit.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 8/12
Then you’ll be presented with a list of the jobs, you’ll want to make sure that the jobs are
passing once you’ve completed the corresponding task.
Filecheck stages ensure that the le exists and has been updated from the default. Test
stages run the submitted les against our tests to measure correctness.
PDF Artifact
Your repo will be packaged into a pdf for marking purposes. As such it is important that you
see what the result of the pdf job is and make sure the output makes sense.
It will:
take your name and uid from the statement-of-originality.md
take images from your exN.dig les
take test results similar to those in the exN.dig les
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 9/12
take references from the statement-of-originality.md
To view the pdf, rst click the ci icon on your most recent commit (as above), then click on
the pdf job.
Then, you’ll be taken to the job page, where you should see a “Job Artifacts” section, click
on the Browse button.
This will allow you to preview your pdf. Which should look something like this.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 10/12
There is more general info about gitlab ci here.
FAQ
My circuits don’t work, can I email you for help?
Sorry, you won’t get help over email or Teams. We provide a course forum which is the only
way we are able to help.
Forum posts related to your assessment submission must be “private” (as for any individual
assessment task).
It’s [5 minutes, 60 minutes, 12 hours] before the deadline and my CI
Jobs aren’t nishing!
Unfortunately on the day that an assessment is due, when many students are pushing
updates at once, the CI servers can’t keep up. You may not see your CI jobs nish before the
deadline. You will just have to manually check that your les have been submitted correctly
and that you are passing tests locally.
The best way to avoid this issue is to start early and nish early
If there’s any issues with your git repository after the deadline. Please let us know (after the
deadline) through a private forum post and there may be something we can do.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 11/12
How do I know my assessment has been submitted?
If:
the les in your fork of the assessment are correct (i.e., the les you intend to submit)
when checking on the gitlab website
the time is before the deadline
then your assessment has been submitted (well done!).
Please don’t ask us to “check”, we would be just doing exactly the same thing as the above
steps which you can do yourself.
Acknowledgement of Country
The Australian National University acknowledges, celebrates and pays our respects to the
Ngunnawal and Ngambri people of the Canberra region and to all First Nations Australians
on whose traditional lands we meet and work, and whose cultures are among the oldest
continuing cultures in human history.
2024/3/9 17:16 Checkpoint 1: Digital Logic | Computer Organisation and Program Execution
https://comp.anu.edu.au/courses/comp2300/assessments/checkpoint-1/ 12/12
Contact ANU
Copyright
Disclaimer
Privacy
Freedom of Information
+61 2 6125 5111
The Australian National University, Canberra
TEQSA Provider ID: PRV12002 (Australian University)
CRICOS Provider Code: 00120C
ABN: 52 234 063 906
