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ELEC3285 Integrated Circuit Design
COMPUTER LABORATORY SESSIONS
Overview

This is intended to be a first of five face-to-face computer lab sessions There may be
7 mentioned in the catalogue – these are 2 extra potential surgery sessions, in which
you should learn how to use an example of a modern chip design and simulation
tool. The learning approach will be largely self-determined learning by using
screencasts and following these instruction sheets and using the associated
manual.pdf for reference.
The final assessment with be worth 30% of the module mark (completed as a series
of 4 personal mini E-Lab Book submissions, beginning after the week 2 session of
the lab. These will be based on use of the resources / links in your Class OneNote
CAD Lab Folder, and submitted by printing the relevant sections and pages to a pdf
in a personal folder and then uploading to Turnitin tool on the VLE. I suggest you
check this process (except for the Turnitin submission which you can do only once
for each journal entry) so you know how to capture everything that you have been
working on. This is your responsibility to get right with respect to the Turnitin
submission.
Using the usual guideline the 3 credits should involve between 20 and 40 hours of
your study time in total using the tool - and that should be sufficient to learn /
understand and use the tool to complete the associated tasks (for some this may
mean only 15 hours for others this could be the full 30-40hours) – but this is a big
component and the marks for this could offset any less good performance in the first
assessment.
The learning intention is that along the way you will employ what we have been
learning and gain a deeper appreciation of both the discipline of integrated circuit
design and with it a deeper appreciation of any related electronics and hardware that
underpins our modern society, which some refer to as the second machine age, or
the 4th industrial revolution.
I particularly favour the former with the first being where humans learnt how to
harness greater and greater mechanical power (advantage) and all the leverage that
that has given to constructing ever larger and more complex (Mega-) structures, and
machines, then in the last 60 or so years we’ve harnessed intellectual and
computational power (the “thinking” advantage) giving us unparalleled access to
information and computational capability to greatly extend our understanding and
control of the world around us, especially for massive and incredibly complex
problems, in this new geological epoch referred to as the Anthropocene.
The computing and associated Bio-tech tools and modelling (computer resources)
underpinning the human genome project, led to the genetic sequencing and vaccine
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development that helped us out of the global pandemic and averted population
collapse that arguably came with similar global pandemics.
To succeed with this CAD design work I’d encourage you to spend a series of one or
two hour sessions on your own on top of the timetabled classes exploring and using
the software (which should be accessible elsewhere on campus – and on your laptop
provided you have already a short-cut on your laptop via apps anywhere and have
pulse secure (VPN) running, and I would rather you take your time individually to
think about what’s really going on with the tool and to learn how to use the tool
efficiently?
This is not a fully functioning professional design tool (which typically might cost
£20k- 30k/seat!) but it is still a powerful design environment enabling hierarchical
design of semi-custom or fully custom application specific integrated circuits, and
shares many of the capabilities with industry standard tools such as Synopsys,
Cadence IC, Mentor Graphics (which collectively are referred to as Electronic design
automation (EDA) tools (or whatever these have morphed into these days) but is
much less complex to learn and use. Incidentally a senior EDA Engineer (probably
with about 10-15 yrs experience or those professional tools) can easily earn 60-
80k/yr in the UK or equivalent elsewhere!
Initially, you should follow the instructions given in each of the accompanying sets of
lab sheets, and this work will culminate in your submitting your own independent
reports and simulation results on a weekly journal.
This year, to ease the assessment burden on yourselves and to help you focus on
using the tool to explore transistor and logic gate design and switching behaviour
rather than on report writing, you will complete an outline report-proforma in the form
of filling in some spaces and comment boxes and adding your own figures and
“measured” data. Maximum marks will be given for correct work and clear and
concise use of graphs and tabulated data and insightful comments. Any one free-text
discussion / answer should require no more than 100-400 words and associated
small tables and illustrations / figures to support your answers.
The first component / Lab session will be a training exercise to learn to use the
software to study the layout and the “switching” of some simple transistors and logic
gates, and to help you begin to understand some of Microwind and DSCH's features
and functionality. The first Journal should be submitted at the end of week 2 of the
lab (12pm Fri 15th March) followed by another at the end of week 3 (12pm Fri 22nd
March)and then the remaining 2 when you restart after the Easter break.
By the end of this first stage, you should have viewed any screencasts and be able
to:
a) Understand some of the capabilities and constraints of chip layout and
simulation tools (Microwind and its sister tool DSCH). Some of the constraints
may seem frustrating but often hide an underlying logic protecting the designer
as they work from breaking some of the technology dependent (foundry) design
rules.
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b) You will begin to see how the transistor layout information, underlying
technology choices and logic gates can be exported and analysed in SPICE
(Simulation Package with Integrated Circuit Emphasis). To see the
consequences of design choices on the switching behaviour of the logic. How
Spice net-lists and Verilog files can be exported and input allowing the
movement up and down the design hierarchy in terms of abstract or physical
levels, and begin to appreciate what the different terms and structures mean. –
You will probably need to look to the web and my lectures for the information
and resources to properly explore and understand these aspects.
c) You will be able to use Microwind and DSCH to set up and analyse simple
transistor circuits and logic gates and explore/evaluate their behaviour and
functionality.
d) Be better placed and ready to use Microwind and DSCH to analyse more
complex circuits.
Over the course of this computer aided design work, you will have a number of tasks
to complete. I’d recommend you independently open and add your simulation results
and conclusions to a word document or your own draft Electronic Lab-book in your
Class OneNote folder as you go through and complete the tasks and questions.
Then you can copy and paste to you final document and then print the sections to a
.PDF document – this is just good practice and will help you complete the pieces of
work which will be assessed.
Your answers to the various questions can be informed by any suitable web source,
book, research paper, or lecture notes, but please do not cut and paste material
from any of these sources – this information should only be used to support your
understanding / learning, for obvious reasons you should not just simply copy or
paraphrase the information, even if you do reference their origin.
At several points, you may wish to include an appropriate screenshot from the
software (windows flag-key+shift+S keys in Windows 10), but remember that there is
some skill required in preparing the figure and adding labels, numbers and axes so
as to convey your work, and you must also explain the basics of any graphs,
tables or illustrations to the reader – this can be done in <50 words and is just
good practice as a professional engineer, and one you should get in the habit of
doing, to explain to the reader the reason for presenting the illustration, as well as
summarising the important details of the illustration, along with any trends and
subtleties (which is where the illustration or graphic really comes into its own in
supporting your discussion). These general skills and practice should have been
developed already, and should also help you to effectively report on the other work
you did on your individual projects.
You should use these exercises to cement (develop these reporting skills to a high
order) to practice presenting good informative graphs or annotated screen-shots.
Please label your answers with numbers (so you can refer back to any figure if you
need to later in your document), and ensure that all pasted figures have captions
explaining what they are showing.
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This first set of hurdles is intended to teach you some of the basic skills necessary in
analysing circuits using Microwind and DSCH. Later components will be more open-
ended, to give you a chance to explore some aspects of the software in more detail.
Tasks to complete in the first phase of the exercise.
1) Introduction

Please use the manual.pdf for Microwind, which is provided on the VLE under the
CAD Exercises & Materials heading. I strongly recommend you create a Word®
document or OneNote draft document, and regularly save screenshots and brief
observations to this document as you move through the tasks.
In the past Microwind has shut-down unexpectedly, and this problem is likely to
happen again as there remains an issue with the floating license, i.e. a latency in the
call and response with the license manager and program set up, and which we have
been struggling to debug / fix. Basically the program is designed as a stand-alone
tool and doesn’t play well over a networked license server – a new version for the
class is £10-15k but there’s no reason to expect it to be all that different license
manager wise. It may be possible for me to negotiate personal time limited copies
that you can download but the supporters for this are based in India and I think this
package (Microwind) is only a very small part of the software that they sell / support..
To access the software it is best to use one of the university’s wired computers and
apps anywhere: (some of this is hard for me to check because I don’t see things the
way a student registration does – so please email me if you have any problems).
1) Start the Pulse Secure VPN tool
2) Find the Program on Apps anywhere and launch it – this should add
Microwind and Dsch to the computer you are using.
3) Another approach from home or a not Windows PC is to add and Run the
Remote Desktop, and log in using your usual University credentials.
4) You may also need to run a VPN session (Pulse Secure) and log in
beforehand, if you are at home.

Fig 1
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5) Double-click the Academic Icon

Fig 2
6) Sign in using your university credentials – you may need to use Duo Push as
a second authentication step – instructions for this are on the IT FAQ pages.
7) Open Apps Anywhere and find Microwind (sometimes it takes a couple of
minutes to go from a black screen to a live desktop)
8) Open Microwind – and all being well, it should come up with the prompt that
the license fully installed (if its going to shut down because of license issues it
usually does within the first couple of minutes!)
9) The Logic Editor Dsch3.5 can be found from the program listing under the
lower left corner window icon – you will need this later, so it’s useful to
remember where this can be found.
10) The opening screen should look like the following

Fig 3

Then
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Fig 4

Dsch3.5 looks like the following – but you won’t need that until a later stage.

Fig 5
11) If it shuts down or fails to open from Apps Anywhere then try resetting apps
anywhere and try again. Sometimes the License Manager and associated
systems reset themselves on a timed basis so try again in a half an hour to an
hour.
12) If from Apps Anywhere Microwind fails to Open and Run, then raise an IT
ticket and Email me to let me know so I can keep an eye on things. –
sometimes the License Server needs to be reset through some physical
intervention – tell-tail sign is “can’t find license manager”, followed by a total
collapse of the software. – so, again, be careful to save your work to a safe
directory once you have invested significant time in some activity.
13) Reminder: When Microwind is Running then using the Windows flag on the
lower left of your screen (of the WVD terminal session that’s running) you
should be able to drop down the list and select the Dsch program.
14) Once you’ve got started please read page 8 of the manual headed
"Introduction" and take the time to explore the various short cuts and menus
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and the drawing pallet, look at the Introduction Screencasts and then answer
the following questions for yourself and add to your word document.
Please note that not all of the answers will be directly given to you in the text; you
should instead use your knowledge of transistor fabrication and design
obtained from the lectures and recommended books to inform and annotate
your studies as well as from other sources where appropriate, to answer the
questions raised: Please also take time outside the scheduled classes to learn how
to use the program and explore the capabilities, which will greatly speed your later
assessed design work.
The General user interface appearance is as follows.

On the top are the main drop down menus – for example second from the right is the
layers pallet shown on the right hand side (rhs). At the top of this pallet there are
some drawing macros / shortcuts, such as to pick and drop some contacts between /
to layers. Below that some component placement shortcuts, including the transistors,
and below those, some macros for setting up the stimulation / clock waveforms and
adding nodes to ground or Vdd or nodes to monitor during the simulation.
This user interface passes parameters to a SPICE-like programme that does the
actual simulation then Microwind reads back the data for graphing the results.
Later I’ll ask you to build some transistors or simple inverters or logic gates and then
from the top-most menu file>Convert Into>SPICE Netlist to view the Netlist (since
SPICE was initially written in Fortran some of the formatting conforms to the Fortran
scripting style.

To familiarise you with Navigating the Menus and user interface try some of the
following and then come back and study what’s actually happened as a result of
these shortcuts.
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Go to file>Select Foundry and open, say, a cmos018.rule – this is a 180nm
technology (you can check this by looking at the top right ruler on the layout screen
where one Lambda = 180/2.
Go to File>Open>Examples>basic gates>Nand2.MSK>Open
Just do it once but below I’ve invoked this shortcut twice and I could if I wanted wire
them. This shortcut is taking a Nand2 from the library (which we refer to as a leaf
cell, or a gate primitive, or an Instance) and dropped it in your design window. This
Instance of a Nand2 is a layout of a 2 input Nand gate primitive, that has been
(probably) optimised for a particular technology, size, speed etc.


Here I’ve opened / inserted two instances of a 2 input nand gate (nand2). – I can edit
these and save, but in so doing I risk overwriting the library file (in principle you
shouldn’t have write access to the remote machine), best not to try it in case it
corrupts the library for everyone else, but you might be able to overwrite your own
library and get horribly confused, when you make subsequent library calls resulting
in corrupted instances! You should save as your own files with your own naming
convention (suggest you use something like Nand_andyourinitials.MSK etc to your
own OneDrive directory under ELEC3285 CAD folder) to your local workspace and
then remember to navigate your way back to the examples folder any time you need
to!).
Note that although not immediately obvious, this 2 input nand shows two PMOS
devices in parallel. – the brown rectangle is the N-type well in which the PMOS
transistor must sit, whilst the bottom NMOS devices are in series. – this observation
is important and follows the usual convention, of having the PMOS at the top (near
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VDD, and to facilitate the N-Tap), and the NMOS at the bottom (near VSS or GND, and
facilitating the P-Tap). This simply requires the n-type diffusion for the source and
drain (into the P-doped substrate) and then the metal gate here forms a self-aligned
mask preventing the n-type diffusion (or implant) from changing the underlying P-
type material in the channel below the gate (which we will later “Invert” to switch on
the transistor). Take a moment to inspect and see that both PMOS sources are
connected to VDD rail. And one of the bottom two NMOS sources which are in series
are connected to Ground or VSS – remember that since these NMOS devices are in
series, so you don’t want both of their sources connected to ground! – the transistor
nearest the output (marked nand2), will have its drain nearest the output and its
source connected to the previous NMOS drain that’s in series, although since they
share the same N+-diffusion (green stripe) there doesn’t need to be explicit contact.
As an aside / reminder, – these IC CMOS transistors are symmetric, and the source
and drain can be interchangeable depending on which direction the carriers are
flowing (i.e. when used as a pass-transistor) but there because of the way they are
explicitly wired then the source and drains are fixed – the source, remember, is the
source of the carriers – in the PMOS case then obviously the current / carriers are
sourced from the VDD rail. For the NMOS transistors the carriers / electrons are
sourced from the ground rail (current still flows to ground but remember the charge
carriers in the NMOS are negatively charged electrons!).
Now inspect the PMOS transistors in parallel and see that how, if their Gates are
alternatively opened (remember this needs a 0 voltage), they will connect the output
node to the top VDD rail so charging whatever is connected to the output.
If you get a bit lost then simply start by opening a new design! .. but importantly, do
not save / overwrite the previous layout, in doing so– similarly if you quit, think
carefully if you want to save present layout to minimise the risks of overwriting
anything important.

Up until now I’ve not drawn your attention to the ability to design in different
technologies – Now look at / load different Foundry’s and in so doing you should get
a new set of design rules, models and library files. Although its possible some of the
gate libraries use generic information, for safety please assume that its only at the
point of loading the instance or leaf cell, that the technology and design rules are
invoked for the respective technology node. – this is another example of hierarchical
design and the use constant field scaling rules, and lambda (λ) based design
methods. Followed by synthesis to move from one level to the next (i.e. Dsch logic
gate representational level, when synthesised moved down in the hierarchy to the
Microwind transistor or layout level using the detail from the design rules) – in this
case from the node based symbol level to a layout / mask level.
From File>Select Foundry>cmos32n.rule –
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This would select a 32nm technology node or process (signified by the n), where the
transistors and components selected would have to conform to the appropriate
lambda based design rules – which would be 2λ = 32nm. If you go to Help>Design
Rules then the dimensions and constraints should be those conforming to the 32nm
technology process node. Inspect also the Contact and other rules (note the
multiples of Lambda lengths and separations. Note also the physical and material
information tabulated under the Summary tab.


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Note how easy, in principle, it is using this hierarchical and standardised approach to
move between technologies and designs using libraries of logic gate primitives.
In principle, by interconnecting leaf cells into larger logic blocks, and then connecting
these together using higher level interconnects (see later 3-D viewing capability) it is
possible to form even bigger, more complex, functional blocks and adding these to
the library. After checking and optimising these leaf cells or (logic) gate primitives,
and including clock signals and memory elements, then it is relatively straightforward
(by which I mean weeks or months of detailed design and testing work) to design a
custom applications specific integrated circuit. Strictly speaking, if you were using a
set of pre-existing library components like this the design approach would be
referred to as semi-custom design.
When developing prototypes, you are most likely to submit your initial designs to a
multi-project wafer fabrication run (a shared design run). With maybe 3-6 wafer starts
per year, costing perhaps between £1k to £20k /mm2 per run, depending on the
challenges of the technology node, and a design could be 1mm2 to 400mm2!, with a
minimum purchase order area of say 5mm2.



Now for this namd2 cell, use the green run arrow to run a waveform simulation –
check its behaving like what you expect of a 2 input NAND gate, note the slew in the
output and the differences between the fall and rise times – we shall explain this later
in class – check the bottom window tab options and note that presently you are in
the Voltage versus time sub-window (some of the tab options may not be appropriate
depending on the logic gate you are studying) and the very bottom reporting line
which summarises some of the important model details from the spice file.
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Figure ? Note: the right hand side dialogue / menu allows you to change the simulation time
window, reset / rerun the simulation even low at a Monte Carlo / parametric simulation with a range
of process or temperature variations

i) With what you have learnt already, and with reference to the manual, what
then are DSCH and Microwind programmes?, how would you describe
these tools to another electronic engineer? i.e. what does each do and
how do their functionality and capabilities differ from the information given
in the manual?
ii) What advantages and disadvantages would you expect of these two
different tools? As design tools in the hierarchical view if IC design?
(if you are unsure of this point, come back to it later after using the physical
description level editor later on).

So far this has just been a glimpse of the functionality of the tool. Next, I want you to
explore what it takes to begin to build and study a library cell of a single transistor.
This is to learn some of the layout capabilities and setting up the stimulation
waveforms and to learn a bit more about the construction of these Enhancement
mode MOSFETS.
This ten credit module is only an introduction and to do this really well, and to an
expert level, you could study this topic exclusively for 3 years (and 360 credits)
during which, as you should already have, you would know the basics as a minimum
of; carrier transport, semiconductor physics, electrical circuits, transistors and their
behaviour and limits / non-linearity in different scenarios, together with digital
electronics, general programming and maybe some power and communications but
with a very much heavier/deeper emphasis on integrated electronics.
Next is a “blow-by-blow” guide to learning how to use the tool.
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2) Background to IC simulation

To make the most of this scheduled session you should skip to part 3), but if you
have time in the end or are making good progress then you can work through this
section.
Later (preferably off-line) you should read pages 17 to 42 of the manual for
background information on "technology scale-down", and the design rules which are
implemented by Microwind, and then answer the following questions:
i) Look at figure 1-2 on page 18. What do you notice about how the relative
permittivity of the gate dielectric is used in integrated circuits, has it changed
over time?

a. Why the change had been necessary? And,
b. What are the improved characteristics which the change has brought
about? (You may need to perform some web searches to obtain this
information as well as go back to look through the relevant sections of the
lecture notes).

ii) The manual states that Microwind has been designed to simulate and design
transistors with "45 nm technology". What does this mean?

iii) What do “Lambda (λ) based design” rules mean? – use Wikipedia or Google
or vlsitechnology.org to learn about this if you do not already know.

iv) How many metal layers does the default technology support and what
separates these alternative metal layers, why is there no mention of the
insulator choices? You can use the technology Summary files to investigate
the differences between technologies / technology nodes.

v) Look at figure 1.8 on page 22 of the manual. The "general purpose" version
of the 45-nm design rules implemented by Microwind is suitable for the design
of a wide range of integrated circuits, but not for the very fast processors on
the right-hand side of the diagram. What variation to the design rules might be
necessary to implement the faster switching of these fast ICs, and what
problems might these changes causes for general purpose (eg. mobile
phone) integrated circuits?

3) Simulating a single transistor - DC characteristics

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Start Microwind by locating it under AppsAnywhere and then thereafter is should run
on your machine from the file menu. In 160 or any other University hard-wired
machine this should be all you need. On a personal machine you may need to run
under WVM (may be slow to connect and run – un-useably so- complain to IT!) or
VPN via Pulse Secure.
FYI: The license server machine lives somewhere on the network and sometimes
the network traffic delays result in the license manager program on the license
server from either not responding or crashing, and if this is the case your local copy
of Microwind will do the same!!. Let’s hope this is not the same this year!!
If this does happen then please understand that this is somewhat out of my control
and IT have been repeatedly made aware of the issue – they will not let me restart
the License server so any delays with restarting the license are somewhat out of my
hands. Note that when there are lots of last-minute work being done for the
CAD reports we have in the past had serious issues with the license
availability, which is why for this year I’m spreading out the submission into
more smaller pieces. The solution is to not to leave your submissions to the
last hours or day of the week. Save your studies / evidence your work / simulations
as you go as screen shots with your commentary at the time (just good practice to
think about – “why did you make this run?, and on what instance were you running
the study on, what were you expecting to “see”?, Did what you saw confirm what you
were hoping to see?, did you learn or spot anything new?, should you change
anything and repeat a new run to check for any expected differences? And what do
you conclude from this mini-study?), and then at the end it’s a simple matter of
compiling tour previous stored work into that final report.
If you are using one of the machines in the CaPE 24hr cluster then Apps Anywhere
should also allow access to what you need, and again the hard-wired connection
should allow the license manager to work well.
Now read and follow the instructions on pages 24-29 of the manual to create and
then simulate the DC characteristics of an n-channel MOS transistor using
Microwind. (NB Figure 2-3 should look like the following, but was omitted from the
manual by mistake!). Remember that the substrate or well in which an n-channel
transistor is formed is p-type (implicitly assumed in Microwind) and that the source
and drain contacts are themselves diffused into this p-type well and that the
presence of the self-aligned gate acts to shield the underlying p-region (under the
gate) from the N+ doping diffusion or implant.
Before creating the transistor you need to select a diffusion layer first, you will need
to do it every time you open micro wind (the default creating a layer is set to TiN
gate). The materials are selected in the “pallet” which can be opened by pressing:

When you cross a diffused region of n-type (greed) or p-type material (brown)
material with a stripe of polysilicon or Titanium Nitride (TiN) Microwind knows
implicitly that you wish to form a transistor. In practice when it actually comes to
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diffusing in (or implanting) the dopants to form the well the polysilicon or TiN stripe
will act as a self-aligned (very important condition) mask and in effect defines the
Source-gate and drain regions of the transistor. Obviously later you will need to
connect contacts to the various regions to get enectrons in and out of the source and
drain and to apply the voltages to the source, gate and drain regions and then
thereafter to (essentially) wire the different transistors together to form the various
logic gates. To minimize drawing errors its best to use the auto-layout capabilities of
the programme where possible (see later compile command) to avoid brealing any of
the layout related design rules (see Help>design rules for related info).
After you finished following the Manual (page 26-27). You should end up with
something like figure 2-3:

Fig 2-3: Creating the N-channel MOS transistor
It does not have to be precise as long as there is an overlap between the materials.
Note that the gate length in the diagram above is the length of the overlapping
orange stripe (note the colour change) between the two green regions (which now
become the n+ doped Source and Drain, separated by the orange overlapping gate
stripe) in the x- direction, and is the length the carriers need to go to get from the
source to the drain. Underneath the orange/red (TiN gate) stripe bounded by the
greed region is the previous p-type substrate – its only the green regions to either
side where the added dopants (by diffusion or ion-implantation) have outnumbered
the previous p-type material (resulting in n-type majority doping - where n-, n, n+ and
n++ represent lightly doped n, intermediate n [~1017], heavily doped n [1018-1019] and
very heavily doped n [1020] or degenerately doped n-type) and the self-aligned TiN or
polysilicon gate masked or prevented the added n-type doping from entering the
region under the gate – this is what meant by self-aligned in this instance. For the
PMOS transistor an N-well (green) is formed first (remember the silicon wafer was
doped p-type to begin with) then the polysilicon or TiN stripe is added (where the
gate will be) followed by the self-aligned p-type diffusion (brown).
If you click on the top transistor characteristics icon:

Then you can see the Ids versus Vds/Vgs characteristics, and by varying the layout
of the transistor, i.e. gate length and width you should be able to see directly the
effect that this has on the predicted electrical behaviour.
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Compare the electrical results using different SPICE models (Level1, Level3 and
BSIM4 – top right tabs of transistor characteristics). You could even try comparing
using two different technology files to the default 45nm (see Help>Design Rules for
more information) with the same gate width (taken from the larger technology width
and think about what is being shown by these comparisons – the learning objective
here is to primarily explore how the transistors (and later Logic gate primitives) react
to design and technology changes. Although the tool (Microwind) may differ from
other tools like Cadence IC or Synopsys it’s the general behaviours and links
between the electrical characteristics and parameters that I want you to appreciate:
i) Try to work out what minimum gate length of the default 45nm technology
and then compare the electrical characteristics of two similar-sized transistors
but realized using different technologies (say the cmos65n versus the
cmos018, or 65n and 45n or 22n).
a. Look at the design rules and the electrical characteristics for the
transistors and compare – does what you find to agree with what you may
expect (from my notes / discussion)?

To access different technology file: file > Select Foundry (or Ctrl+F).


Insert a screenshot into your word document of the calculated transistor
characteristics obtained using the default parameters from the simulation and;
ii) Comment on what you see and what you expect when you vary the length
and width of the TiN stripe. You are best redrawing the green box (n-diffusion)
and red stripe (TiN gate) each time.

iii) Describe the influence of gate voltage on the source / drain current. How
would you expect this to alter for different values of the gate width and length?

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a. I.e. create three different gate widths, each in a separate simulation, to
check whether your expectation was correct.
(NB the easiest way to reset Microwind is simply to exit without saving changes and
then restart, but you could also just increase the width of the red box by clicking the
stretch icon and then the side of the box to make it bigger, before re-simulating).

iv) Check also on one of your designs the effect of increasing the threshold
voltage and then the temperature and see if things change as you expect –
comment on the result and explain why you think this is happening.
There are also tabs at the bottom of the screen to select between low leakage,
high speed and high power. (still in the “transistor characteristics” graph)
v) Select the different options and comment on the different parameters on the
far right of the screen such as oxide thickness (TOXE), the Threshold
voltage (VTHO), etc. and how they are linked to the design performance i.e.
high speed or low leakage.
Look at the transistor characteristics (Id Vs Vd and Threshold Voltage etc) and try to
understand and explain what the different traces show.

vi) Insert a screenshot of the cross-section of one of your transistor geometries
obtained using the "process section in 2D" command, as discussed on
page 26 of the manual. Check the cross-section looks similar to that shown in
Figure 2-4 (if it doesn't, ensure that you are selecting the "horizontal" rather
than "vertical" cross-section!

To select “process section in 2D” you click on the symbol:


And then move it across the whole transistor length (from left to right).
Page 18 of 21



4) Simulating a single transistor - transient characteristics

Follow the instructions on page 28 and 29 of the manual.
NB you may find that the "default" clock applied to the drain does not correspond to
that shown in Fig. 2.7, in which case adjust the drain clock parameters by clicking on
the drain to adjust them.
i) Insert into your Word document a screenshot of the transient device
characteristic you obtain. Describe in your own words what the
transients characteristics show.

a. Discuss any artefacts and where they may come from and why the
peak voltages on the sampled node vary the way they do, i.e. why
does the voltage on the sampled 5 nodes not rise to the expected
value why for different time periods of the gate may the voltage be
different?
Page 19 of 21

Try to understand what’s going on in general terms and for specific conditions – i.e.
just use the tool to explore what’s going on by using the trial waveforms given below,
note that larger transistors or transistors drawn using a different technology may give
different DC and transient characteristics to those of your neighbour. Not all the tabs
will be relevant on all occasions.
After you finish the practice task in the manual, and have added the various
nodes in your ab-initio (new) design, and set the stimulation and analysis (watch)
attributes, then set the gate and drain voltages to the values provided below and
capture the results. Note: for some of the smaller nodes 45n, 32n,22n these
switching transients may not be aggressive enough to “see” the slew-rate associated
with different gate widths, Wg, or loads.
i) The values for Vgate and Vdrain.
a)
VGate: Time Low: 0.125ns Rise Time: 0.001ns Time High: 0.175ns Fall Time: 0.005ns
VDrain: Time Low: 0.022ns Rise Time: 0.001ns Time High: 0.033ns Fall Time: 0.001ns
b)
VGate: Time Low: 0.125ns Rise Time: 0.001ns Time High: 0.275ns Fall Time: 0.005ns
VDrain: Time Low: 0.022ns Rise Time: 0.001ns Time High: 0.033ns Fall Time: 0.001ns
c)
VDrain: Time Low: 0.125ns Rise Time: 0.001ns Time High: 0.175ns Fall Time: 0.005ns
VGate: Time Low: 0.022ns Rise Time: 0.001ns Time High: 0.033ns Fall Time: 0.001ns

Try typing the drain to VDD rather than applying a series of clock signals (leave the
clock signals as before) and;
ii) Comment on the maximum voltage seen on the source – how does this
relate to the threshold voltage? – look back at the behaviour of pass-
transistor logic in the lecture notes.
You may also want to explore the effect of the different models (Level1, Level 3 and
BSim4) on the transient and static response.
iii) What do you think is the difference between the different models?
If you are really keen then convert your transistors into different spice model netlists
and try to explore the meaning and significance of the different terms, you may need
to use the extract button to effect any changes.
iv) What is going on there during this extract process?
i.e. link back to my simple formula, discussed in the lectures for the threshold voltage
etc. What do you think the process variations>Monte-Carlo tool is doing, what help
does this provide for the designer?
v) What does the CIF layout convert tool do?
Page 20 of 21


5) P-channel MOS device

Open the file "pMOS.msk" from the example folder (under “open file” in Microwind
you can look in the examples folder for the mos\Pmos.msk file). Open the file in
Microwind. In order to not to temper with the given examples, make a copy of the file
you want to work with into your created module folder.
Investigate the cross-section of the device, and say how it differs from the n-
channel MOS device already investigated above.
i) Simulate the DC and transient characteristics, and confirm whether your
expectations are correct (you should include a screenshot of both the DC
and transient characteristics in your discussion). What is different about
this transistor?
How to find examples.


Page 21 of 21

6) Extension activity

If you finish all the above in good time, you can use the pallet menu and use the
transistor layout generator (MOS generator) to generate different sized N-MOS
and P-MOS transistors and study their characteristics and you could even try
building an inverter that way.
You can also open the various .msk files in the basic gates folder such as the Nand2
or InvFanout1 and have a play to see their behaviour and what the layout looks like
and perhaps even start to investigate the effect of channel geometry on the
simulated transient characteristics (either the n-channel device or the p-channel).
i) Alter the width and length of the channel and determine the effect this has
on the transient characteristics, documenting your investigation as you go
along.

You can also look at the 3D fabrication simulation from the N+ well formed on the
silicon to the thin oxide and etched thin oxide then the polysilicon gate as a means to
begin to understand the fabrication sequences, which I’m afraid you will cover
properly until next year but I’m happy to answer questions in class about this.
You may also choose, as mentioned earlier to start looking at the characteristics of a
more realistic/complex circuit, such as an inverter or a transmission gate. An
example layout file for an inverter can be found in the file "invNmos.MSK" in the
Examples\inverter directory.
i) Load this file and investigate the DC and transient characteristics,
discussing what you find.
Similarly, you can use the compile command to layout some simple logic gates – say
a 2 or 3 input NAND or NOR and check the functionality and compare to what is
expected for the truth table.

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