ELEC3280 Integrated Circuit Design
Exercise
COMPUTER LABORATORY SESSIONS
Part 2 The beginning of your Individual Assignments (each worth 10% of the Module Mark)
The Previous CAD laboratory instructions were aimed at an introduction to the software and
its capabilities, without being too serious about using it as an investigative tool.
It is ok to work together on this (I’d even encourage you to discuss this amongst yourselves)
but when it comes to the assessed journal / Lab Book submissions you must present your
own studies and understanding as evidence of your work. Likewise I’m looking for your own
interpretation / links to the notes or sections of the recommended books. Such use of notes
and references must be in your own words / descriptions rather than a copy, to avoid any
risk of plagiarism. Beware also, that if you use non-English search engines and translation
tools, then it’s very likely these will result in the same links and translations as other
students. It is extremely unlikely that where the simulations have been undertaken properly
and independently, even when using similar models, conditions and simulations, that you
would get exactly the same results as anyone working with you, so just bear this in mind
when writing your reports.
Appendix1: discusses the shape of the assignments
You should find the screencasts very helpful as a guide to using the software and
approaching the exercises.
To successfully complete this section (the detail in tasks 5 to 9), you should have learnt how
to navigate your way around the various menus and some of the capabilities of the tool. It is
important that you have used the tool to study how the transistor characteristics for the
individual NMOS and PMOS transistors depend on the gate width (i.e the foundry /
technology node resulting in the family of transistor curves (IDS versus VDS,VGS and
associated transient characteristics (VDS versus VGS versus Time, i.e. the rise and fall time of
the voltage at the output node). Take time to understand the very important difference
between the gate length and the gate width (the effect of each on the teansistor
characteristics – it may be helpful to add different values of capacitance to the output node).
Take the time to observe and understand how the material parameters and other variables,
such as gate dielectric thickness, material (i.e. permittivity) affect the threshold voltage and
leakage as determined by the technology chosen, and the result can be seen in the IDS
versus VVDS, VGS family of curves as well as the Log scale plots that more clearly show
the off-leakage. Try this for different foundries / technology nodes. You can also see these
changes in the simple logic gates such as an inverter or 2 input NOR or NAND gates. For
the transistors you can see the effect on the electrical characteristics using the
predetermined variants (or simulation selections in the right side menu), such as low or high
voltage, high speed, and, alternatively the low leakage variations.
What do you think is being changed here when you choose these quick re-
evaluations? –

Check when running these alternatives, what the difference is to the electrical parameters
and characteristics and check which physical variables that have changed resulting from
these quick re-evaluations.
In this and following weeks I want you to consolidate this understanding and extend your
knowledge of the tool to simple logic gate operation and begin to use it to explore in more
detail the concepts that I’ve been lecturing about. I.e. in terms of the construction and
electrical behaviour of current CMOS devices – in particular the switching behaviour and
noise margins of an inverter, and then later come more complex but still simple devices.
My intention for this work is that the investigations should be led by yourselves in the form of
an annotated study (i.e. using your own initiative once you are familiar with the tools and
based on your subject understanding), together with any supporting screencasts.
As your experience with any CAD tool progresses, I suggest you begin to think about and try
to understand the “under-the-covers” limitations or assumptions that any such CAD
environment may use. i.e. what confidence have you that what you are doing is correct, and
how can you test that your designs/test are valid? What checks if any have you made to
build confidence in any result? Does what you see agree with expectations from the
literature / past work, and how might you present this to a boss?
This self-critical approach is exactly the same as partitioning and troubleshooting any
software or hands-on electronics or embedded system build so you can build up confidence
in the final result be piecewise testing and validation.
Any advanced engineering projects, where CAD and EDA tools (Electronic Design Aids or
Electronic Design and Analysis) are used to undertake complex designs and problem solving
(analysis), require an intimate understanding of both the problem as well as the use of the
design tools, and in particular their limitations. This is all part of the process / practice we are
trying to experience here.
Please use a word document or OneNote page to drop screen-captured images, together
with your annotations (of the screenshots) and notes. Remember, a picture or graph is of
limited use if you don’t discuss what you are using the figure to illustrate and any key
subtleties / trends or features of your graphs or screenshots. There have been, and will be
further, opportunities to ask questions during the discussion sessions (Tuesday’s) and queue
up questions via the team’s class chat area. Try also to find the answers yourself from my
lecture notes, the manual for the tool and/or the web. I can then clarify any problems /
questions raised. You should aim to add/build on any new knowledge yourself by exploring
further using the web or lecture notes to “own” this knowledge for yourselves. – you would
be expected to do this in a job, so the aim is to cross-examine as much as you can for
yourself.
Your word document (or OneNote workbook – which is great when capturing paragraphs
from web sources as it leaves an automatic link back to the source for later reference) is a
means of capturing your progress, understanding and thought processes as you progress
through the work. – there’s a good chance that after three to four sessions (hours work), that
if you go back and repeat what you have been asked to do, that it will take a fraction of the
time and can greatly improve upon this first pass whilst adding to your overall understanding.
Only through repeated use of the tool and the screencasts will this make more sense. These
activities will also give you a view into the some of the “low-level” work of the professional IC
design community, re the overall design hierarchy.
The investigations / exercises below, overlap and follow on from the previous instruction
sheets (which are on the VLE), and I’m keen for you to understand as much as possible of
what lies behind what you’ve been asked to explore.

When requested to do so, you can use the data or screen plots captured in your word
document or OneNote workbook to help complete the various sections in the lab-book
proforma suggestion supplied later. In this I’ll be looking for you to demonstrate your
understanding of the behaviour reviewed. The plan is that you will have the supporting
material already generated and observations already to hand (and backed up!) from your
previous studies. You should then be able to quickly and complete the marked exercises,
and submit your word-to-pdf reports via the Turnitin tool on the VLE by 12pm Monday the
18th March. Remember that in general, for any good report, you need to explain / comment
on what any tables, graphs or screenshots show, together with the conditions used to
generate the screenshots or data to demonstrate your understanding of the topic and use of
the tool. Each brief explanation accompanying a figure should only take between 100 and
200 words..
Stage II focussed exercises:
Use Microwind to explore the factors which influence the transistor (and logic gate) leakage
and switching behaviour (DC and transient) of the transistors and the simple leaf cells / gate
primitives upon which they are based.
Microwind allows you to look at the effect of geometry (layout), foundry technology node,
material choices, model variables etc., and to explore this lower level (layout and leaf-cell /
gate primitive design) as an aspect of hierarchal design. Then a designer can go on to
optimise and for populate a gate/cell library. In the industry this is often referred to as
Instantiate or Instantiation, Eg for symmetrical switching, or speed, or layout area.
Now you can begin to see and understand how, at higher levels (more abstract viewpoint), a
designer might then use these instances, or bigger modules – which can themselves be
instantiated, in a component library “pick-and-place” fashion. This is an example of regularity
and reuse, mentioned at the beginning of the module as part of a hierarchical approach.
If you find that you have easily completed all of the material, then you should use any extra
time to revisit any of the questions and augment some of your answers with more detailed
understanding / studies. i.e. making additional predictions and evaluations of the electrical
characteristics by performing suitable simulations, or by investigating the behaviour and
details for more of the many files available under the Microwind / Examples directory.
Overall this exercise will be worth 40% of the module mark and forms a key learning aspect
of this IC design module, with the implication that you have devoted somewhere between 20
and 40 hours on the exercise in total.
When you are fully up to speed and properly familiar with the tool and the content of the
exercises and related lectures, then it should only take an hour or two, to complete each
report, leaving the other 15-35 hours to learn the tool and explore the underlying concepts
from the lectures.
I) (follow-on from prev Lab sheet) More detailed study into the behaviour
of the Enhancement mode MOS Devices (should take no more than 2
hours)
Use the top button bar icon to simulate a generic (foundry dependent example) transistors
(nMOS and pMOSfor two significantly different technologies {Gate lengths}). Look at the low
leakage and high speed, and the high voltage variants and comment on the differences.
Look also at the on and off currents and IDS for the different devices and different Gate
Widths – remember if you are comparing different technologies then using the same gate
widths would be more helpful. – Use the tool’s various capabilities, try to get a better
idea, and show / discuss, what’s going on at the transistor construction level,
together with the trade-offs between leakage and threshold, carrier type (mobility),
temperature, spice model level (complexity), and accuracy etc. and how these relate to
the technology and transistor features.
From the Microwind examples’ folder, copy "pMOS.msk" and “nMOS.msk” into your module
folder – or you can use DSCH to create one and import it. I think the nMOS may be missing
from the examples folder, but you should be able to quickly translate the pMOS layout to
draw your own nMOS transistor (but remember the nMOS used an N+ diffusion for the
source and drain and does not need to sit in a p-well as the assumption is that the substrate
is p-type.
i) Investigate the cross-section of the device, and explain how it differs from the n-
channel MOS device and discuss the various materials used and what their
properties are and why used.
II) i.e. the electrical effect of these choices – use the 2D viewer (found to the right of
the ruler icon on the top button bar) and;
III) A horizontal cross-section (via mouse clicks on the appropriate area) to give a
cut through the different layers of a single transistor.
III) Compare this with the 3D view, you can use the auto or your mouse on the
screen to rotate the 3D view.
This activity will help to give you a really good idea of what the structure of your transistor
looks like from the top (plan view), side (cross-section view), and in 3D.
Seen in 3D, the most important understanding to retain, is how the various levels of
interconnect metals and dielectrics are combined for something like an inverter or 2-input
gate in a Manhattan style layout. – In the tool the interposing (in-between) dielectric material
has been rendered transparent or invisible, and it may not be able to discern (see) the
different conductor track thicknesses, widths and insulator thicknesses. But all this detail can
be found if you learn where to look. The spice models (generated behind the scenes) will
use these values to accurately calculate the overlay capacitances and track resistances as
part of the fan-out calculation. Try capturing some of the screenshots to remind you and to
facilitate your revision / understanding of these aspects.
I would encourage you, and as an extra, to help fully complement your understanding of how
the electrical behaviour, layers and connectivity, results from the processing steps, to try
viewing the simulation of the process steps / layers. To do this, use the icon to the left of the
3D icon for a simple nMOS or pMOS transistor, and step through the process steps both
manually and automatically. To see the sequence of process steps and compare with your
memory of the 2-D cross-section and the 3-D viewer and my slide from lecture 2 showing the
build-up of layers and steps..
Look at the “process step” list on the right-hand side of the screen. These steps are unique
to this particular process but are, in general, the same basic sequence of events for most
silicon microfabrication. An outline idea, of the sequence of events, helps complete your
understanding and appreciation how we make these integrated circuits through the build-up
of hundreds of individual steps and layers. – These processes and approaches are a direct
result of the ~10+ billion person hours that have collectively gone into the understanding and
manufacturing over the last 70 years, to put these smart phones and super computers within
your easy reach. I.e. Physicists, Material Scientists, Chemists, Computer Scientists, Optical
Engineers, Instrument Manufacturers and others.
The basic sequence is :- An initial wafer-wide diffusion or implantation of a base level of
doping. Followed by a layer of thin (gate) oxide (SiO2 or high-k) followed by a thick (field)
oxide, then a polysilicon or polysilicon and metal gate layer. These Gate stripes then define
the self-aligned source/drain regions (determined by the “as-drawn” gate length), followed by
the source and drain diffusion or implant doping step. Then the (low resistance) contact pads
to the source, drain and gate are defined, followed by successive layers of insulator (oxide of
low-k), contact vias, and metal (check the metal layer widths as you go to higher layers).
Each of these steps requires a mask or reticle for patterning (~£1,000 to 10’s or even 100’s
of thousands each,- depending on the resolution). A photo-resist coating step and a UV
exposure stage (similar to the old fashioned B&W-Negative development and printing) using
this shadow mask followed be either a material subtraction (etch), or a material addition
(deposition) stage. Then, often, an intermediate polishing (chemical mechanical polishing
CMP) stage to planarize everything (to a sub-nm rms (root mean square) flatness). – In
short, one layer step may involve 5 or more other intermediate processes before moving to
the next. Use the manual, the process viewer tools, and web sources to explore what this
single transistor looks like and how it is made, and I’m happy to answer questions on these
aspects as it was my profession before returning to academia.
II) A more detailed study on the effect of transistor geometry on transient
effects (should take no more than 3 hours)
Obviously the Transient (switching) effects are hugely dependent in the DC characteristics
investigated above, and the effect of channel geometry on the simulated DC and transient
characteristics (either the n-channel device, nMOS, or the p-channel device, pMOS).
i) How would you expect a p-channel device’s electrical characteristics to differ
from those of the n-channel device if both devices were the same length and
width?
In my lectures, I mentioned two “second-order effects”, associated with the very high fields
developed near the drain side of the transistors, one relating to carrier drift velocity, and one
relating to scattering, energy loss and the generation of additional carriers.
ii) Can you see evidence of any of these effects manifested in the transistor’s
electrical characteristics and leakage, when you change the transistor
dimensions or technology?
iii) If you haven’t done so already, simulate the DC and transient characteristics
of either an nMOS or pMOS transistor (you may have in advertently made
something we call a pass transistor – it’s a stretch to call it a logic gate but it
does crop up very often in the implementation of digital logic and in multiplexors
etc), and with the transient characteristics explain the pass transistor problem
that you should witness – discussed in an early lecture.
With the pMOS.msk or nMOS.msk files loaded and drawn on the screen, you will notice that
the button bar transistor characteristic short-cut and the run arrow to show the
characteristics for the live transistor and you can modify the gate length and width and view
the consequences directly.
iv) Confirm any expectations from changing the transistor type or dimensions (see
next section) are correct.
You should include a labelled screenshot of both the DC and transient
characteristics in your discussion along with the transistor used.
The DC characteristics are dependent on the layout, as it alters the channel resistance. You
can’t “see” the inverted channel depth, but you may infer this (in relative terms) from the
relationship between the channel resistance and the gate voltage and threshold voltage. It is
possible to get a feeling for this with some rough calculations by hand for the channel on
resistance.
v) Alter the width and length of the channel and determine the effect this has on
the transient characteristics, documenting your investigation as you go.
(NB the "length" of the channel means (for IC’s) the distance between the source and drain,
while the "width" of the channel means the width of the path of current flow between the
source and drain).
vi) Describe any observed effects on the transient characteristics and the likely
reasons.
vii) For the top marks and understanding use the File>convert into>spice netlist
and comment on what you see in the listing: i.e. what has the tool just done?
why is this action / capability helpful or necessary? Explain in quite general
terms what the different parts of the netlist imply / show (Without going into
exhaustive levels of detail, unless you have plenty of time). – You may need to
do some searching on the web to aid your understanding - as I’ve not explicitly
discussed this in class – Ming-Bo Lin discusses SPICE netlists).
Again, for the highest marks you should look at the models, parameters and process
variations and comment on why this sort of information is valuable in this context and for
leaf-cell design and optimization. In principle, at least, you could use some of these variables
and some of the formulae from my lectures to explore the differences between hand
calculated values and those from the simulator – some variables may need to be guessed at
or found by working backwards by fitting these simple formulae values to get an agreement
with the CAD simulations.
Appendix 1: The shape of the final in-class assessment
In your Journals / Lab Book Submissions I expect ….
In preparation for this report, I want you to work through the above tasks from this exercise
and which follow on from the Introduction.
To help you to further contextualise the earlier investigations, and as a rough guide, in
general terms, as to how each of the final individual reports will be assessed is summarised
below.
1) Technical content (8 marks).
a. How well / comprehensively you have investigated and reported on the tasks
- In terms of broadness and depth and using what illustrations you have
given, and ideally links back to the lectured material, i.e. the underpinning
relationships and dependencies between the electrical characteristics
(switching speed, leakage etc) together with the technology and layout ?
b. Have you been able to demonstrate a satisfactory use of the tool and
underlying understanding and exploited some of the capabilities of the tool,
and completed the tasks with reference to the concepts covered in the lecture
material - which the numbered lab tasks are structures to guide you to
explore.
It should be possible to give brief answers and explanations with appropriate and suitable
supporting illustrations. For top marks (>7/10) then you should be able to demonstrate the
following:
A more comprehensive and systematic use of the tool, along with a greater understanding of
the underlying concepts. Be able to present your own evidence, where these relationships
were proven or otherwise. – i.e. where your expectations have not been proven. These
unexpected results are not necessarily evidencing a “wrong” answer, the key is that you
discuss your expectations and observations and try to reason why there may be any
disagreements and what you might do to investigate this if you have more time / resources?
2) Presentation and style (2 marks).
a. How comprehensive, thoughtful and clearly presented is the discussion /
evidence, and how well are the important underlying concepts described.
b. In preparing your documents, your answers to the questions should be
informed by any suitable web source, book, research paper, or my lecture
notes. Please avoid the risk of accusations of plagiarism, which can arise
from simply cutting-and-pasting materials from any external sources! Instead,
please reinterpret material and use your own words to discuss the topics
called for in the answer.