Department of Electrical Engineering and Electronics
ELEC373
Digital Systems Design
Assignment 4
NIOS II
Module ELEC373
Coursework name Assignment 4
Component weight 20%
Semester 2
HE Level 6
Lab location PC labs 301, 304 as timetabled, at other times for private study
Work Individually
Timetabled time 15 hours (3 hours per week – Tuesday 9am - noon)
Suggested private study 10 hours including report writing
Assessment method Individual, formal word-processed reports (Block diagrams and
ASMs can be hand drawn and scanned into the report)
Submission format Online via CANVAS
Submission deadline 23:59 on Monday 13th May 2024
Late submission Standard university penalty applies
Resit opportunity August resit period (if total module failed)
Marking policy Marked and moderated independently
Anonymous marking Yes
Feedback Via comments on Canvas
Learning outcomes LO1: Ability to design digital systems using the ASM design method
LO2: Ability to implement digital systems using the Verilog Hardware Description
Language
LO4: Ability to implement a SOPC system using Quartus Nios II.
2
Marking Criteria
Section
Marks
available
Indicative characteristics
Adequate / pass (40%) Very good / Excellent
Presentation and
structure
20%
• Contains cover page
information, table of contents,
sections with appropriate
headings.
• Comprehensible language;
punctuation, grammar and
spelling accurate.
• Equations legible, numbered and
presented correctly.
• Appropriately formatted
reference list.
• Appropriate use of technical,
mathematic and academic
terminology and conventions.
• Word processed with consistent
formatting.
• Pages numbered, figures and tables
captioned.
• All sections clearly signposted.
• Correct cross-referencing (of
figures, tables, equations) and
citations.
Introduction,
Method and
Design
40%
• Problem background introduced
clearly.
• Evidence of a Top Down Design
approach
• Conceptual Design Choices
introduced.
• Design of each module follows a
logical sequence.
• ASMs correspond to designs for
each block.
• Software is clearly commented
• Appropriate range of references
used.
• Design decisions justified with
alternatives given.
• Calculations shown in full, justifying
and explaining any decisions.
• Correct ASM Syntax used.
• Well-structured Verilog Code
Results 30%
• Simulation results present for
each block and well annotated.
• Results of full system in both
simulation and experimentally
presented.
• Results for each task
accompanied by a commentary.
• Screen shots of results
presented.
• Tests indicate that there are no
problems caused by asynchronous
inputs.
• Clear explanation of how the
instructions operate correctly
Discussion 10%
• Discussion on what worked and
what didn’t.
• Critical assessment on the
design – strength and
weaknesses
• Discussion on how the system was
fully tested.
3
ELEC 373 Assignment 4 (2023-24) Synthesising the NIOS II Processor
Assignment Outline
In Assignment 3 you added some extra instructions to a MIPS processor which was then synthesised
and executed on the DE2 board. This assignment aims to introduce you to a commercial synthesised
processor targeted for Altera FPGAs, which allows the easy importing of peripherals and the use of
an industry standard IDE for software development.
Assignment 4 is split into two parts, Parts A and B. The objective of Part A is to get you familiar
with QSYS, the NIOS II Processor and interfacing SRAM and SDRAM, on the Altera DE2 Board,
to the NIOS II processor you synthesise. Part B requires you to develop and test a Custom
Instruction that will be implemented in the FPGA.
Part A – SRAM & SDRAM
The NIOS II hardware development tutorial synthesises a NIOS II processor with, 20 KB of on-chip
memory, a timer, a JTAG UART, 8 parallel I/O pins and a system ID Component. Part A of this
assignment requires you to interface the 512 KB SRAM and 8 MB SDRAM on the Altera DE2
Board to this design.
You should then test that the memory is functioning correctly by running the Memory Test programs
available within the NIOS II IDE. You should modify the Memory Test Programme so that your
Name and ID number are shown in the terminal window each time the memory is tested.
Hints
1. Initially use the altera_up_avalon_sram Controller (SRAM/SSRAM) for the SRAM interface
2. Use the SDRAM controller for the SDRAM Interface
3. Add a PLL to advance the clock for the SDRAM by 3ns compared with the system clock.
Part B – Custom Instruction
Part B requires you to develop a Custom Instruction to count the number of leading 1s (or 0s – see
Table 1) in the 32 bit number passed to the instruction (for example 0xFF000000 would have 8
leading 1s and 0 leading 0s, whilst 0x00F00000 would have 0 leading 1s and 8 leading 0s). You
should write a program to test your Custom Instruction. You should also develop a test routine in C
or assembler that performs the same function as the Custom Instruction and compare the speed of the
Custom Instruction against your software implementation.
Submission
You report should include the following:
1. Block diagram of BDF developed in Part A.
2. Table showing memory Map for Part A
3. Screen dumps of test results showing memory test programs working for SRAM and
SDRAM
4. ASM(s) and Verilog code for your custom instruction in Part B
5. C/C++ for your test program of Part B
6. Screen dump showing the results of your program for Part B
7. Results showing a speed comparison between the Custom Instruction and your software
implementation.
8. Explanation of your results.
Submission Deadline
CANVAS: Monday 13th May 2024 @ 11:59pm
4
Table 1 Part B Custom Instruction Task
ID Name Counting
201563687 Al Meraikhi, Turki Leading 0s
201579371 Alzeyara, Saoud Leading 0s
201503123 Bounds, Dominic Gregor Leading 1s
201676076 Cai, Xinghu Leading 1s
201556978 Cardwell, Stephen Leading 0s
201676131 Chen, SHI Leading 0s
201341221 Desmond, Con Patrick Leading 1s
201676280 Feng, Yiming Leading 1s
201676288 Fu, Yongchuan Leading 0s
201556875 Gardiner, joshua Leading 0s
201511440 Gill, harvey Leading 1s
200956435 Glover, Aaron Phillip Leading 1s
201676340 Guan, Jiale Leading 0s
201676397 He, Zhengyang Leading 0s
201676470 Huang, Zijian Leading 1s
201676486 Jia, Yuming Leading 1s
201676496 Jiang, Jiakun Leading 0s
201676499 Jiang, Qingyuan Leading 0s
201676555 Lam Po Tang, Justin Leading 1s
201676564 Li, Bohang Leading 1s
201676567 Li, Derun Leading 0s
201600584 Li, Yiyuan Leading 0s
201676658 Liang, Chen Leading 1s
201676684 Lin, Shaowei Leading 1s
201676686 Lin, Wenhao Leading 0s
201676707 Liu, Ke Leading 0s
201676808 Ma, Xuheng Leading 1s
201676815 Mao, Haolin Leading 1s
201551565 McCue, Francis Leading 0s
201654980 Mohamad Zaid, Asyraaf Asyraaf Leading 0s
201536424 Pan, Jiachen Leading 1s
201676865 Peng, Yukun Leading 1s
201676889 Qiu, Chufan Leading 0s
201676892 Qiu, Minhao Leading 0s
201676902 Rabetokotany, Toavina Haingotiana Leading 1s
201563996 Reade, Brandon Stuart Leading 1s
201676945 Shen, Yixiao Leading 0s
201472463 Smith, Will Leading 0s
201676987 Su, Zihan Leading 1s
201522294 Sun, Bin Leading 1s
201677013 Sun, Zhijia Leading 0s
201677015 Tan, Lige Leading 0s
201677106 Wang, Siheng Leading 1s
201677116 Wang, Xinyi Leading 1s
201677124 Wang, Xirui Leading 0s
201677148 Wang, Yanchang Leading 0s
201600972 Wang, Yihang Leading 1s
201384487 Wu, Zijia Leading 1s
201677291 Xu, Xiufa Leading 0s
201677298 Xu, Yankai Leading 0s
201677359 Yang, Yang Yi Leading 1s
5
201677430 Zeng, Zhijie Leading 1s
201677437 Zhang, Baicheng Leading 0s
201677450 Zhang, Haoran Leading 0s
201677461 Zhang, Jinsong Leading 1s
201677467 Zhang, Keying Leading 1s
201677471 Zhang, Mingyu Leading 0s
201677575 Zheng, David Leading 0s
201677619 Zhu, Changwei Leading 1s
201639455 Zhu, Zhiyuan Leading 1s
J.S. Smith 25/3/24