Matlab 2012/PFGA ISE 14.4代写-ECTE433/ECTE833

ECTE433/ECTE833: Embedded Systems
FPGA Design Project

Due date: Thursday, 14 May 2021, 16:30 AEST (Week 10)
Assessment weight: 20%
Total marks: 20 This project allows you to practice the FPGA design skills learnt in the lectures, laboratories and tutorials, as there is no better and more exciting way of understanding the material than applying it to solve a practical problem. The project has two tasks: Task 1 is compulsory for all students, whereas Task 2 is optional and attracts bonus marks.
Project Task 1: Integer Divider (compulsory, 20 marks)
Division is an essential but difficult operation in embedded systems. In integer division, the relationship between the inputs (numerator and denominator ) and the outputs (quotient Q and remainder R) can be described as
= × + , where ,,, and are all unsigned integers and 0 ≤ ≤ ሺ − 1ሻ. The numerator is also known as dividend, and the denominator is also known as divisor. For background information on integer division, see https://en.wikipedia.org/wiki/Division_algorithm. This project requires you to develop a high-speed FPGA design for integer division.
• The device has three input signals: ‘N’, ‘D’, and ‘start’.
• Signals ‘N’ and ‘D’ are unsigned integers. The bit-width of ‘N’ and ‘D’ is W bits, where W is a parameter specified in the PreLoadFcn function of the Simulink MDL file. W can be set to 8, 10, 20, 32 and so on.
• Signal ‘start’ is a Boolean variable. When signal ‘start’ goes HIGH, calculation should begin. It is assumed that signal ‘start’ will not go HIGH again until calculation is completed.
• The device has four output signals: ‘Q’, ‘R’, ‘valid’, and ‘clock_count’.
• Signal ‘Q’ is the quotient, and signal ‘R’ is the remainder. They both have a bit-width of W.
• When the device finishes calculating ‘Q’ and ‘R’, it should make the Boolean signal ‘valid’ go HIGH for exactly one clock cycle.
• Output signal ‘clock_count’ should store the actual number of clock cycles used for calculating ‘Q’ and ‘R’. For example, if calculation starts at clock cycle 2 (‘start’ = HIGH), and finishes at clock cycle 20 (‘valid’ = HIGH), then ‘clock_count’ = 20 − 2 = 18.
• The design must be created using MATLAB Simulink and Xilinx System Generator. The following built-in Xilinx blocks must not be used: Divider Generator, Divide, Black Box, MCode, Mult, CMult, Natural Logarithm, Reciprocal, and Square Root.
• Xilinx ISE version 14.4, MATLAB 2012b, Windows 7 or 10 64-bit are the assumed platform.
Q
R
clock_count
valid
N
D
start
FPGA
Page 2 of 3
On Moodle, there is a template file ‘Project_Template.mdl’ that contains the necessary input/output ports and start-up parameters. While you are free to move the existing input and output blocks in the template file, do not modify their parameters. Rename the template file to the form of ‘Project_StudentID_Surname.mdl’ and start your work. For example, for student Jay Beta, ID 1122333, the design file should be ‘Project_1122333_Beta.mdl’.

Table 1: Testing the integer divider.
Test Case W N D Q? R? 1 8 18 3 6 0 2 8 18 7 2 4 3 16 1350 5 270 0 4 20 202103 9 22455 8

Create also a text file with name ‘Project_StudentID_Surname.txt’ that stores information about your design’s performance (clock counts and the numbers of Xilinx blocks). The file should have the following format where the blue text is relevant to your submission. Adhere to the strict formatting because during project marking, this file will be first processed by a computer program. Student = Jay Beta Student ID = 1122333 Clock count for Task 1 Test Case 1 = 15 Clock count for Task 1 Test Case 2 = 16 Clock count for Task 1 Test Case 3 = 20 Clock count for Task 1 Test Case 4 = 30 Number of Mux blocks = 2 Number of Counter blocks = 2 Number of AddSub blocks = 2 Number of Register blocks = 9 Number of Concat blocks = 3 Number of Slice blocks = 5 Number of Relational blocks = 5 Number of Logical/Expression/Inverter blocks = 5 Number of Delay/Constant blocks = 2
Design competition
• To encourage outstanding efforts by students, a design competition is organized and the top 5%, 10%, or 15% solutions for Project Task 1 will be awarded extra 3 marks, 2 marks, or 1 mark, respectively. These solutions should also be at level-5 in operation, algorithm, and presentation (see Table 2).
• The competition criterion is the processing speed. Firstly, submissions are short-listed according to the number of clock cycles (clock_count) used to process the test cases in Table 1 (Note: Designs entirely based on the table-lookup approach are not acceptable). Secondly, an undisclosed test case will be used to select the competition winners.
• When two submissions have the same speed, ranking is based on the quality of presentation and the resource usage.
Page 3 of 3
Project Task 2: FPGA Graphical Application using VHDL/Verilog (optional – 3 marks) Develop a graphical application to be run on the Spartan-3E Starter Kit. You are free to choose which application to implement. It should involve writing VHDL or Verilog code for the FPGA board to interact with at least the VGA monitor and one input device. The input device can be the keyboard or the mouse. Example applications (graphic games) are shown at: http://www.uow.edu.au/~phung/teach/ecte433/FPGA_tetris.avi http://www.uow.edu.au/~phung/teach/ecte433/FPGA_roachwars.avi
• This project task is optional. Students who are able to complete this project task will be awarded extra 3 marks.
• For this project task, study ‘Spartan-3E Starter Kit Board User Guide’ and other resources available on Moodle. Search also the Internet for reference VHDL/Verilog code for the Spartan 3E Starter Kit.
Marking guide The project will be marked out of 20 using the rubric shown in Table 2. This is not a group project. Submitting work that is not your own will result in a mark of 0 and other penalties according to the University Rules. Letting other students copy your work will result in the same penalties.

Table 2: Marking rubric for the project.
Design
Aspect
Performance Band
Level 0 (0%) Level 1 (20%) Level 2 (40%) Level 3 (60%) Level 4 (80%) Level 5 (100%)
O
pe
ra
tio
n
(8
m
ar
ks
)
Lacks necessary
design blocks.
Does not
execute.
Executes but
produces
significantly
incorrect outputs.
Requires some
modifications to
work.
- Works most of
the time, except
for some test
cases.
- Some output
signals are not in
the required
format.
- Works perfectly.
- Performance file
(TXT) is correctly
recorded.
- Meets all design
objectives.
A
lg
or
ith
m

(8
m
ar
ks
)
Algorithm is
fundamentally
flawed.
Algorithm
requires
substantial
corrections.
Algorithm is
either slow or
inefficient.
Algorithm is fast
but its
implementation
contains
extensive
redundancy.
Algorithm is fast
but its
implementation
contains some
redundancy.
- Algorithm is
highly optimized
for both speed
and resource
usage.
- Better than or
equivalent to the
sample solution.
Pr
es
en
ta
tio
n
(4
m
ar
ks
)
No visible effort
to document the
design.
Some visible
effort, but still
poor
presentation.
- Blocks/wires are
Too many
crosses.
- Some
used, but content
is superficial.
- Blocks/wires
could be
arranged better.
- Do not follow
submission
guidelines
(formatting, file
names, contents)
- Blocks are
generally laid out
with care.
- Main signals are
given meaningful
names.
should be clearer
and more
concise.

- Concise, clear
used.
- Design is
described clearly.
- Blocks are
intelligently
organized.
- Suitable use of
sub-systems.
submission
guidelines.
Submission
• Log onto Moodle site for ECTE433 and ECTE833.
• For Project Task 1 (compulsory), submit two files: ‘Project_StudentID_Surname.mdl’ and ‘Project_StudentID_Surname.txt’. Use the relevant StudentID and Surname for you.
• For Project Task 2 (optional), submit file ‘Project2_StudentID_Surname.zip’ that contains ISE project file, source code, BIT file, and readme.txt. File readme.txt briefly describes the graphical application and the steps to test it.

Have fun designing!