CSSE2010/7201 - Introduction to Computer Systems
Assignment 1: Digital Logic Design
Semester 2, 2025
Due date for Blackboard submission 05/09/25, 4:00pm AEST.
Demonstrations during scheduled lab sessions in week 7.
This assignment will be marked out of 36 and is worth 18% of your overall course mark. Revision 1.1
Design and Verification Task
You are required to design, implement, and test a digital circuit which can count the number of 1’s present in
an incoming serial bit stream. Here, for simplicity, the incoming bit stream is limited to 16 bits, composed by
using the 4-bit unsigned binary representation of the last four decimal digits of your 8-digit student number.
For example, for the 8-digit student number XXXX1234, the 16-bit input stream becomes 0001︸︷︷︸
1
0010︸︷︷︸
2
0011︸︷︷︸
3
0100︸︷︷︸
4
(such a representation is also known as the binary coded decimal (BCD)). The proposed circuit must process the
incoming bits serially to output the total number of 1’s present in 4-bit unsigned binary format (5 = 01012 for
the above example). In order to test the circuit using switches, buttons, and LEDs available on the IO board, the
inputs, outputs, and functionality of the system must adhere to the following. Consider the student number of
form XXXXN3N2N1N0, where N0,1,2,3 ∈ {0, 1, ..., 9}.
• The overall circuit has an input processing subsystem followed by a serial addition subsystem (see Fig. 1).
• The input processing subsystem (block A in Fig. 1) employs 4-bit parallel load and serial shift operations
to enter the 16-bit input as four batches of 4 bits. The user sets the mode selector switch S7 = 0 to enable
parallel load, then sets the switches S3 − S0 corresponding to the 4-bit binary version of N0, and provides
a clock pulse by pressing and releasing the B0 button (on the IO board). This loads the first digit N0 into
the system. The user then sets the mode selector switch S7 = 1 to enable serial shift and provide four clock
pulses by pressing the button B0 four times. This completes the serial shift for the first digit N0. This
process (i.e., parallel load and serial shift) is then repeated for other digits N1, N2, N3.
• The serial addition subsystem (block B in Fig. 1) takes one bit at a time from the input processing subsystem
and adds this incoming bit (either 0 or 1) to an accumulated sum. Therefore, the serial addition subsystem
may contain an adder to perform the addition and a storage element to store the accumulated sum.
• After 20 clock pulses (1 clock pulse for parallel load and 4 clock pulses for serial shift for N0 and repeated for
N1, N2, N3), the 4-bit output of the serial addition subsystem, connected to IO board LEDs L3 − L0 must
show the total number of 1’s present in the 16-bit input. Eg, if N0 = 610 = 01102, then the count displayed
should progress 0→ 1→ 2→ 2 over the first four clock cycles after the value is loaded.
• The system also has a reset switch input on S5, which resets all internal registers to 0.
Figure 1: System-level circuit topology depicting inputs, outputs and subsystems A and B.
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Your task is to design the above system and verify its functionality by constructing the circuit on breadboard. You
can only use logic ICs provided in your CSSE2010/7201 lab kit and the overall circuit can be implemented with a
total of 4 logic ICs. You will be assessed based on a Blackboard submission followed by a practical demonstration.
The Blackboard submission includes several questions which require you to provide logic diagrams for subsystems
A and B and a schematic diagram for the overall design. Prior to attempting circuit construction, you may
optionally simulate your design in Logisim to verify its functionality. However, no marks will be awarded for
Logisim simulations. If you don’t achieve a fully functional circuit, for the practical demonstration, you have the
option to demonstrate the functionality of the subsystems A and B separately using the intermediate inputs and
outputs indicated in dash lines in Fig. 1.
Blackboard Submission
You are required to submit answers to several questions using the submission template given in pages 3-5 of this
document. The submission template containing the questions will be also made available as a separate document
on Blackboard. You must submit a single PDF file named as A1 xxxxxxxx.pdf, where xxxxxxxx is your 8-digit
student number, and must be submitted electronically to Blackboard according to the exact instructions listed
on the Blackboard website. The due date for Blackboard submission is Friday, 05/09/25, 4:00pm AEST. You
must use the provided submission template for this submission.
You can submit your assignment multiple times before the deadline but only the last submission before the deadline
will be marked. Only submit the PDF file as described above. You are responsible for ensuring that you have
submitted the files that you intended to submit. You are encouraged to download your submission from Blackboard
and ensure it contains the correct files.
Submitted work should be neat, legible and simple to understand - you may be penalised for work that is untidy
or difficult to read. While you can collaborate to clarify any doubts in the learning material required for the
assignment, the work you submit must be your own and this is an individual assignment. During the practical
demonstration, you may be asked to explain your solutions to teaching staff.
Late Penalties: A penalty of 10% of the maximum possible mark will be deducted per 24 hours from time
submission is due for up to 7 days. After 7 days, you will receive a mark of 0. More details available on the ECP.
Practical Demonstration
As part of this assessment task, you are expected to demonstrate the functionality of your implemented circuit.
You must construct and test your circuit prior to attending the demonstration.
During your practical demonstration, you will be allocated to arrive for a block of 15-25 minutes during one of
your two regularly scheduled practical sessions for week 7. More information about your exact demonstration time
slot will be communicated to you on Blackboard.
You will be expected to arrive on time, enter the room, and await instructions from the the the teaching staff. You
will be given 5 minutes to setup, power your circuit and perform some quick testing before your demonstration
begins. During the demonstration, teaching staff will first ask some preliminary questions based on your Blackboard
submission. You will be then asked to demonstrate the functionality of your circuit. To assess your understanding
and implementation, you may be requested to demonstrate alternative inputs to your system (such as a different
4-digit number than the end of your student number). Subsequently, there will be some follow on questions about
the operation of the circuit.
Attendance Hurdle: Should you fail to attend your allocated demonstration time during week 7 (without a
valid extension), you will be offered an opportunity to attend a make-up demonstration later in the semester and
have your mark capped at a maximum of two-thirds of the total available marks (24 marks). Should you again fail
to attend the make-up demonstration, your mark will be capped at a maximum of one-third of the total available
marks (12 marks).
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Submission Template
You must use this document template to complete the Blackboard submission. A separate PDF of this template
will also be available on Blackboard.
Student Details
Full Name
Student Number
Assigned Demo Time
Practical Demonstration [15 marks]
I have completed and will be demonstrating (please tick one of the three options),
□ Only the Input Processing Subsystem (Block A)
□ Only the Serial Addition Subsystem (Block B)
□ The full system (Blocks A and B)
Design Reasoning [4 marks]
Review the task brief, Fig. 1 and any relevant course content. For each subsystem shown in Fig. 1, mention the
combinational/sequential circuit blocks required to implement the given functionality and identify the correspond-
ing logic ICs from your lab kit. When mentioning the circuit blocks, your answer must include specific details
about input sizes and number of blocks needed. E.g., three 2-input NAND gates, one 2:4 decoder etc.
Input Processing Subsystem [2 marks]
Serial Addition Subsystem [2 marks]
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Logic Diagrams [10 marks]
Provide logic diagrams for each of the subsystems using the circuit blocks identified above. Logic diagrams can
be either hand-drawn or electronically produced and must fit within the space provided below. Logisim screenshots
are not accepted as Logic diagrams. All inputs and outputs must be labeled with the same names as shown in
Fig. 1 and the diagrams must adhere to conventions taught in CSSE2010/7201.
Input Processing Subsystem [5 marks]
Serial Addition Subsystem [5 marks]
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Circuit Schematic [7 marks]
Provide a circuit schematic diagram (either hand-drawn or electronically produced) for the overall system by
integrating the two logic diagrams above and mapping the circuit blocks to logic ICs available in your lab kit.
Ensure that you are accurately following all conventions of circuit schematics. You may rotate the page.
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