ECE GY 6913 Computing
Systems Architecture
RISCV Simulator Project – Phase 2
Spring 2026
Goal of the Project
● Have a working model of a 32 bit RISC-V interpreter.
● Accurately maintain the values in all registers and
memory locations.
● Project is to be done either in Python or C++. The
boiler-plate code will been provided on brightspace.
● Project is to be done individually.
Grading Scheme and support
● Weightage of the RISCV project will be 10% of your total grade.
● Each phase (Single stage and Five stage) will be out of 50 marks
● Test cases – total 10 – 3 of which will be released a week before submission of each phase.
● Project report – contains questions and marking scheme which will be posted on Brightspace
● Phase 2 submission is on 1st May 2026
Input
imem.txt
contains binary input of all the instructions
dmem.txt
contains binary input of all the memory locations
Output
Performance Metrics
Register States after each cycle
DMem at the end of program execution
State Results
What needs to be done in IF
Read 4 lines of the IMEM file.
What needs to be done in ID
Convert the 32 bits into an instruction. (Big endian)
00000000
01010010
00000001
10110011
Instruction: 00000000010100100000000110110011
Decoded instruction: add x3, x4, x5
What needs to be done in EX
Instruction: add x3, x4, x5
lw x10, 20(x12)
Be sure to perform the right execution at this stage.
R and I type instructions will perform the normal executions.
Load and Store instructions will perform calculations of offset.
What needs to be done in MEM
Make sure to access memory in this stage.
LOAD and STORE instructions
What needs to be done in WB
Update the values of registers in this stage.
Eg. loading a value into a register, arithmetic result to be written into
register
Instructions to be implemented
Please refer Brightspace Project document which contains all instructions that need to be
implemented.

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