arm代写-APRIL 2020
时间:2021-04-19
APRIL 2020
Final Examination
Computer Organization
ECSE324, section 001
April 24th, 2020, 9am
EXAMINER: Christophe Dubach ASSOC. EXAMINER: Boris Vaisband
STUDENT NAME: McGILL ID:
EXAM:
CLOSED BOOK ☐ OPEN BOOK x
SINGLE-SIDED x PRINTED ON BOTH SIDES OF THE PAGE ☐
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EXTRA BOOKLETS PERMITTED: YES ☐ NO x
ANSWER ON EXAM: YES ☐ NO x
SHOULD THE EXAM BE: RETURNED x KEPT BY STUDENT ☐
CRIB SHEETS:
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CALCULATORS:
NOT PERMITTED ☐
PERMITTED (Non-Programmable) x PERMITTED (Programmable) ☐
ANY SPECIAL
INSTRUCTIONS: e.g.
molecular models
Course: Computer Organization, ECSE324 Page number: 1 / 14
Important information, please read it in full
Communication embargo: Please remember that you are not allowed to
communicate (online or offline) with anyone else about the content of this exam
until the end of the exam (24h after the start time). If anyone tries to get in
touch with you during this period to discuss the content of this exam, please report
it immediately by email to the instructor (chrisotphe.dubach@mcgill.ca).
Response format: This PDF version is provided as a backup and should only
be used in case you encounter issues with the online quiz on mycourses. If you
decide to use this PDF for your exam, please return all your answers in a text file
(no photo/scan) before the end of the exam. Each answer should be correctly
labelled with the proper number from the corresponding question in the PDF. For
answers requiring to fill in a table, simply use colons to separate the columns and a
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1 2 3
4 5 6
is written as:
1, 2, 3
4, 5, 6
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McGillid_Firstname_Lastname.txt
where you replace Firstname, Lastname and McGillid with your specific information.
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In addition, please make sure to read and copy/paste the following text
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By submitting this work, I certify that the work represents solely my own efforts. I
confirm that I understand the meaning and consequences of cheating, plagiarism
and other academic offences under the Code of Student Conduct and Disciplinary
Procedures, and am aware of my responsibilities under the Student Assessment
Policy.
Course: Computer Organization, ECSE324 Page number: 2 / 14
1) General knowledge [ total 16 points]
Short questions, [ 1 point ] each. For multiple choice questions, circle your
choice. If more than one is circled, you will get zero for that question.
1.1) Given a byte-addressable memory and a 24-bit address space, the
maximum capacity of the memory is:
a) b) c) d) e)
4MB 16MB 4GB 16GB None of these
b
1.2) Consider a machine with a memory alignment of 8 bytes. Which
addresses are valid to use to access a half-word?
a) b) c) d) e)
2 4 6 All of these None of these
d if assumed 4 bytes word, b if assumed 8 bytes word.
1.3) Which register contains the address of an instruction?
a) b) c) d) e)
CPSR IR PC SP None of these
c
1.4) Assuming an 8 bit processor and the content of R1 is 00110011. The
content of R2 after executing ASR R2, R1, #2 is
a) b) c) d) e)
00110011 11001100 00000011 10001100 None of these
e
1.5) Which instruction might modify the CPSR (Current Program Status
Register)?
a) b) c) d) e)
TST CMP ADDS All of these None of these
d
1.6) Order these components in the order they are usually run:
Loader, Linker, Assembler
Assembler → Linker → Loader
Course: Computer Organization, ECSE324 Page number: 3 / 14
1.7) The KIN status flag in the keyboard status register indicates whether
an input is ready to be read by the CPU. Assuming that this register is
memory mapped, which instruction would you use to check the value of KIN?
a) b) c) d) e)
TST CMP SUB OR None of these
a
1.8) In general, an interruption service routine can:
a) be executed at any time
b) disable interrupts
c) be interrupted
d) All of these
e) None of these
d
1.9) In the context of I/O buses, tri-state buffers are used:
a) to connect a single device at a time to the bus
b) to arbitrate between different bus masters
c) exclusively by asynchronous buses
d) All of these
e) None of these
a
1.10) From the CPU point of view, a DMA controller:
a) is just another I/O device
b) keeps the CPU free to run other instructions during data transfer
c) wakes up the CPU with an interrupt once the transfer is finished
d) All of these
e) None of these0xe59f 0014
d
Course: Computer Organization, ECSE324 Page number: 4 / 14
0.001Short questions, [ 2 points ] each.
1.11) Explain in 2-3 sentences, and in your own words, how a DMA
controller maximizes data throughput on a PCI bus and which feature does it
rely on to achieve this.
Setup start address and length to initiate transfer. Then CPU can do other
things. Wake up with an interrupt. Relies on interrupt.
1.12) Explain in 2-3 sentences, and in your own words, why are serial
links more suitable for longer distances and less expensive.
Less wires implies cheaper (less material). More stable over long distance,
less problem with timing issues (parallel bus required careful
synchronizations).
1.13) Explain in 2-3 sentences, and in your own words, why some CISC-
processors use an interconnect network between the different hardware
components (e.g. ALU, Register File, Memory interface, …) while RISC
machines do not need an interconnect network.
The CISC machine instruction’s input and output come from / go to many
different components. So everything need to be connected. In contract, RISC
instructions are much simpler and all data come from / go to the Register
files for arithmetic instructions or Memory interface for memory instructions.
0xe59f 0014
Course: Computer Organization, ECSE324 Page number: 5 / 14
2) Assembly [ total 16 points]
Assume an 8-bit processor with a byte-addressable memory and with the
following set of instructions together with their semantic and bit encoding.
MOV Rd, #imm // Rd imm ← (immediate value)
0 Rd : 2 bits imm : 5 bits
BLT Rs1, Rs2, Raddr // branch to [Raddr] if [RS1 < Rs2]
1 0 Rs1 : 2 bits Rs2: 2 bits Raddr: 2 bits
LD Rd, Raddr // Rd [MEM[R← addr]]
1 1 0 0 Rd : 2 bits Raddr : 2 bits
ST Rs, Raddr // MEM[Raddr] [Rs]←
1 1 0 1 Rd : 2 bits Raddr : 2 bits
ADD Rd, Rs1 // Rd [R← d] + [Rs1]
1 1 1 0 Rd : 2 bits Rs1: 2 bits
MUL Rd, Rs1 // Rd [Rd] * [Rs1]←
1 1 1 1 Rd : 2 bits Rs1: 2 bits
We will also assume the following encoding for registers:
R0 = 00, R1 = 01, R2 = 10 and R3 = 11.
Consider the following program.
VEC: .byte 1,2,3,4,5
MOV R0, =VEC
MOV R1, #1
MOV R3, #3
LOOP:
LD R2, R0
ADD R2, R1
ST R2, R0
ADD R0, R1
MOV R2, =LOOP
ADD R2, R3
BLT R0, R3, R2
Course: Computer Organization, ECSE324 Page number: 6 / 14
2.1) Given the binary encoding specification above, complete the symbol
table below for the program given. Please note that some rows might be not
be used in the table. Remember, this is an 8-bit processor.
[ 2 points ]
Symbol Name Symbol Value
VEC 0x00
LOOP 0x08
2.2) Given the binary encoding specification above, complete the table
below for all memory addresses listed. Op Code/Data should be expressed in
binary. If the Op Code / Data is undefined, please state so. [ 6 points ]
Memory Address Op Code / Data
0x00 00000001
0x01 00000010
0x02 00000011
0x03 00000100
0x04 00000101
0x05 0 00 00000
0x06 0 01 00001
0x07 0 11 00011
0x08 1100 10 00
0x09 1110 10 01
0x0a 1101 10 00
0x0b 1110 00 01
0x0c 0 10 01000
0x0d 1110 10 11
0x0e 10 00 11 10
0x0f undefined
1 pt for 0x00, 1pt for 0xf. 4 points for addresses [0x01-0x0f], -1pt for any
wrong answer.
Course: Computer Organization, ECSE324 Page number: 7 / 14
2.3) What is the content of the memory for the vector Vec at the end of the
execution? [ 2 points ]
VEC =
2 2 3 4 5
1pt for Vec[0], 1pt for the rest.
2.4) Using a combination of instructions from the set given above,
implement the following pseudo-instruction: [ 3 points ]
B Raddr // branch to [Raddr]
MOV R1, #0
MOV R2, #1
BLT R1, R2, Raddr
2.5) Using a combination of instructions from the set given above,
implement the following pseudo-instruction: [ 3 points ]
BEQ Rs1, Rs2, Raddr // branch to [Raddr] if [RS1] == [Rs2]
BLT Rs1, Rs2, =continue
BLT Rs2, Rs1, =continue
MOV R1, #0
MOV R2, #1
BLT R1, R2, Raddr
// valid alternative instead of 3 instructions above
// B Raddr
continue:
Course: Computer Organization, ECSE324 Page number: 8 / 14
3) Memory [ total 16 points ]
Here is the internal organization of an asynchronous dynamic memory chip
(DRAM).
3.1) Assume the Data signal is 4 bits wide. Indicate what is the minimum
width required for each signal below (number of bits). [ 7 points ]
Signal Number of bits
Address 11
Row_address 11
Col_address 11
Word_lines 2048
bit_lines 8192
bit_lines’ 8192
CAS 1
Course: Computer Organization, ECSE324 Page number: 9 / 14
3.2) Indicate the direction of the following signals (using a combination of
East,West,South,North). For instance, the direction of Address is East while
the direction for Data is North&South. [ 3 points ]
Signal Direction
Word_lines East
bit_lines North&South
bit_lines’ North&South
3.3) You are being tasked with designing the control logic to refresh the
DRAM above. Assume the Sense/Write circuits has a latch to store a row and
that the control logic has direct access to the signals below to perform its
task. Which of these signals are not needed by the control logic?
[ 3 points ]
address
CAS ← not needed
RAS
Data ← not needed
CS
R/W
3.4) Explain in 2-3 sentences, and in your own words, what is the
advantage of having a latch to store a row and how is this feature called?
[ 3 points ]
Can use the same row multiple times for consecutive reads of elements in
the same column. This is called fast page mode.
Course: Computer Organization, ECSE324 Page number: 10 / 14
4) Cache [ total 16 points ]
Consider the following ARM assembly program. The first column corresponds
to the address (in decimal) where each data/instruction is stored in memory.
The second column contains assembly labels while the third column contains
assembly instructions or directives. The last column contains, for each
instruction, it’s representation in hexadecimal.
Address Label Instruction/Directive Encoding
00 VEC: .word 0,1,2,3,4,5,6,7
32 start: LDR R0, =VEC 0x e59f 0014
36 MOV R1, #0 0x e3a0 1000
40 loop: LDR R2, [R0,#4]! 0x e5b0 2004
44 ADD R1, R1, #1 0x e281 1001
48 CMP R1, #8 0x e351 0008
52 BLT loop 0x baff fffb
56 B start 0x eaff fff8
Consider the following cache configuration:
- 2-way set-associative
- Block size is 4 bytes
- Cache size is 32 bytes
- Least-recently-used replacement policy
4.1) Consider a dedicated first level (L1) data cache (only data from load or
store operations are cached). [ total 8 points ]
4.1.1) What is the content of set 0 of the cache (show both ways) after
instruction at address 56 (B start) executes for the first time?
[ 2 points ]
0xe59f 0014 4
4.1.2) What is the content of set 0 of the cache (show both ways) after
instruction at address 56 (B start) executes for the second time?
[ 2 points ]
0xe59f 0014 4
Course: Computer Organization, ECSE324 Page number: 11 / 14
4.1.3) Assuming instruction at address 56 (B start) has executed 100
times, what is the total number of misses? [ 2 points ]
8 (2 points)
If mistakenly assumed LDR R0, =VEC is a Load (VEC is small, the LDR pseudo
instruction is actually a MOV): 306 (1.5 points)
4.1.4) Assuming instruction at address 56 (B start) has executed 100
times, what is the cache miss rate in percentage? [ 2 points ]
8/800 = 0.01 = 1% (2 points)
If mistakenly assumed LDR R0, =VEC is a Load, 34% is correct (1.5 points)
4.5) Now, consider a first level (L1) unified cache. A unified cache can store
both instructions and data without discrimination. Assume that right before
an instruction executes, the instruction is loaded from memory into the
cache if not already present. [ total 8 points ]
4.5.1) What is the content of set 0 of the cache (show both ways) after
instruction at address 52 (BLT loop) executes for the first time? [ 2 points ]
e351 0008 0
4.5.2) What is the content of set 0 of the cache (show both ways) after
instruction at address 52 (BLT loop) executes for the second time?
[ 2 points ]
e351 0008 0
4.5.3) When instruction at address 56 (B start) is reached for the first
time, how many hits in the unified cache? [ 2 points ]
28
4.5.4) When instruction at address 56 (B start) is reached for the first
time, how many misses in the unified cache? [ 2 points ]
14 correct answer could also be 15 (depending on whether we assume 56 (B
start) has executed or not (2 points)
if mistakenly assumed LDR R0, =VEC is a Load, 15. (16 is also correct if we
assume 56 (B start) has executed). 2 points)
Course: Computer Organization, ECSE324 Page number: 12 / 14
5) CPU [ total 16 points ]
The datapath and control signals of a CPU are given below.
5.1) Assuming you are dealing with an ARM machine, where are the
condition signals connected to? [ 2 points ]
CSPR (current status program register)
Course: Computer Organization, ECSE324 Page number: 13 / 14
5.2) Explain in 2-3 sentences, and in your own words, why the Return
address is an input to the MuxY multiplexer and why is LINK an input to the
MuxC mutiplixer. Hint: think of an instruction that uses these two signals and
include this in your explanation. [ 3 points ]
BL (Branch and link). Link register is in the register file. Content of return
address can be written into the register file by setting C_select to select Link
as destination address.
5.3) Given the following instruction, ADD R1, R2, #4, what is the content of
the following signals at the different stages?
Assume that this is the only instruction being executed by the processor. If
the signal is unknown or not relevant for that stage, leave it empty. For the
register file addresses, use the register name directly (e.g. R1).
[ 11 points ]
Stage 2 Stage 3 Stage 4 Stage 5
Address A R2
Address B
Address C R1
RF_Write 0 0 0 1
C_select 0
B_select 1
Y_select 0
Except for RF_Write,
- 1.5pt per signal if the row is entirely correct
- 1pt if signal value is correct but misplaced or repeated
For RF_write:
- 2pt if row is entirely correct
- 1pt if first value is 0 and then 1 (misplaced or repeated)
- 0.5pt if the only value is a 1 ( misplaced or repeated)
Course: Computer Organization, ECSE324 Page number: 14 / 14











































































































































































































































































































































































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