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IC集成电路代写-ELEC 372 /-Assignment 3

时间：2021-04-20

Integrated Circuit Design Assignment - 1

ELEC 372 / 472: Integrated Circuit Design Assignment 3

Objective

To understand fundamental concepts underlying CMOS gate speed and power

performance, as covered in ELEC 372/472, in the context of design. To design, verify and

investigate CMOS standard cells conforming to the specified design rules using a

professional, integrated circuit design package, named Cadence.

For guidance, a 15 credit module unit is meant to occupy 150 hours in total (including

both private study and contact hours). You should aim to spend about 3-4 hours per week at

the terminals. The remainder of the time will be taken up with background reading and

research.

KEEP A LOG BOOK OF YOUR PROGRESS.

EFFECTIVE TIME MANAGEMENT IS A KEY SKILL THAT APPLIES TO

ALL PROFESSIONS AND WORKING SITUATIONS.

SO IF YOU GET STUCK, ASK – DO NOT WASTE TIME – STAY FOCUSED

Any queries email below.

Dr. K. Hoettges: k.hoettges@liverpool.ac.uk

Integrated Circuit Design Assignment - 2

Section 1 - Design another 2 input NAND gate (Total marks 30)

Design another two input NAND gate with a capacitive load, CL (You can reuse your code

from assignment 1 do calculate this or appendix A2). The NMOS devices should have a

width of 6um and a length of 3um. The width of the PMOS devices should be equal to the

number assigned to you and length = 3m. The value of CL should reflect the widths of the

NMOS and PMOS devices. Investigate the rise/fall times when the width of both PMOS’s

and also the widths of each NMOS device are varied. Repeat the above and adjust the value

of CL to compensate for the increased widths of the new transistors.

In your report:

Record and comment and explain your results (refer to lecture notes or literature!)

In assignment 1 we model an inverter not a NAND gate, discuss why we can use this to

get an adequate value for CL?

Section 2 - Investigate the power dissipation of the loaded CMOS inverter (refer

to A3). (Total marks 30)

• Using your ‘matched’ value of Wp, employ the ‘power meter’ circuit of appendix 3,

and plot the power dissipation over 5 or more cycles (rise and fall times) of the input

signal. Plot input and output voltage waveforms; drain current of p-MOST and n-

MOST and power dissipation of the DUT on the same page but as separate traces. (10

marks)

• Devise a simulation that allows separation of dynamic power dissipation and short

circuit current power dissipation. Comment on the relative magnitudes of the two

components. Repeat the simulation at a lower frequency and compare the results to

those of the higher frequency. Change the width of the p-MOST to be the same as in

assigned to you in assignment 3 (Look on Vital) and analyse the dynamic and short-

circuit current power.

▪ Quote power consumption in both ‘watts’ and as ‘ energy per transition’.

▪ Check that the values you are getting are sensible. (20 marks)

In your report:

Record and comment and explain your results (refer to lecture notes or literature!)

Explain how the power meter circuit works.

Integrated Circuit Design Assignment - 3

Section 3 - Design a clocked SR Flip Flop and fully test by simulation (Total marks

40)

To design the clocked SR flip flop you should link together the circuits you have already

designed in the previous sections – (Keeping your assigned gate width – marks will be

deducted if this is not the case-). You can place your previous cell layouts in your new layout

by using create/instance. Only add the interconnects to connect the cells together.

Test the circuit with Spectre and then join together your original layout cell views to create a

new complete layout view. You should then and run the DRC am LVS to ensure there are no

errors.

In your report:

Include a printout of the simulation results, the cell views , LVS and DRC and layout in

your report. Comment and explain on your results.

Report:

Please write a report covering all the main design steps and considerations and theory.

Please explain your results – Just stating what happens is insufficient. Use and explain

suitable truth tables for testing. Add screen grabs of schematic, layout and simulation

results where suitable. Remember that only a completed LVS and DRC validate your

layout.

Integrated Circuit Design Assignment - 4

Appendix 1: DRC rules

Design layer rules 1.5um

Drawn layer 1: Active area

1.1 Min. width 1.5

1.2 Min. spacing 2

1.3 Min. spacing to scribe 25

Drawn layer 2 : Pwell

2.1 Min. width 4.0

2.2 Min. spacing 14.0

2.3 Pwell to P+ Active area 3.0

2.4 Nwell to N+ Active area 3.0

2.5 Pwell enclosure of N+ (P+) Active area 3

2.6 N-field enclosure of P-well 3

Drawn layer 4: Polysilicon

4.1 Min. width 1.5

4.2 Min. spacing 2.0

4.3 Min. spacing of gate field from active area edge 1.0

4.4 Min. gatepoly extension over active area edge 1.5

4.5 Min. width of source/drain region 2

4.6 Min. spacing to scribe 25

Drawn layers 5/6: P+/N+ diffusion

5.1 Min. width 2.5

5.2 Min. spacing 1.5

5.3 D/S terminal overlap of active area 1

5.4 Overlap of N+/P+ for butt contacts 0.5

5.5 Overlap of S/D for gated diode 0.5

5.6 P+ spacing to unrelated N+Active Area 1.5

5.7 N+ spacing to unrelated P+Active Area 1.5

Drawn layer 7: Contacts

7.1 Min/Max. width 2.0x2.0

7.2 Min. Spacing 2.0

7.3 Min. spacing of gate poly contact to active area edge 2.0

7.4 Min spacing of active area contact to gate poly 1.5

7.5 Min. enclosure by Active area 1.0

7.6 Min. enclosure by gate poly 1.0

7.7 Min. spacing to scribe 25

Drawn layer 8: Metal 1

Integrated Circuit Design Assignment - 5

8.1 Min. width 3

8.2 Min. spacing 2.0

8.3 Min. overlap of contact 1.0

8.4 Min. spacing to scribe 25

Drawn layer 9: Via

9.1 Min./Max. width 2.0

9.2 Min. spacing 2.0

9.3 Min. enclosure of metal 1/metal 2 1.0

9.4 Min. spacing to active area edge 1.5

9.5 Min. spacing to gate poly edge 1.5

9.6 Min. spacing to contact 1.5

9.7 Stacking via over contact is not permitted -

9.8 Min. spacing to scribe 25

Drawn layer 10: Metal 2

10.1 Min. width 3.0

10.2 Min. spacing 2.0

10.3 Min. overlap of via 1.0

10.4 Min. spacing to scribe 25

2um (DRC 7.3)

1um1um

2.0um (DRC 7.1)

1um (DRC 4.3)

2um 1.5um

2um (DRC 4.2)

(DRC 4.5) (DRC 4.1)

1.5um (DRC 4.4)

(DRC 7.5) (DRC 7.4)

= contact

= polysilicon

= N+ diffusion

= active area

Integrated Circuit Design Assignment - 6

LSW window

Selected layer for drawing

Text dg Text layer - cosmetic

M1Q dg metal 1

M2Q dg metal 2

AAQ dg active area

PLQ dg polysilicon

PWQ dg P well

NFQ dg N-field

PPQ dg P+ doping

NNQ dg N+ doping

V1Q dg via

CTQ dg contact

OSC dg outer schematic layer – cosmetic layer

ISC dg inner schematic layer – cosmetic layer

M1Q pn metal1 pin

M2Q pn metal2 pin

DEM pn DEM pin layer – used for “subvdd!”

Integrated Circuit Design Assignment - 7

A2: How to estimate the load capacitance, CL

CGDOn

CGDOp

CGSOp

CGSOn

CGp

CGn

Cdbp

Cdbn

Vin

Vout Vout2

CW

VDD

Figure A2.1 – Unity fan-out inverter

The figure shows a CMOS inverter loaded with another inverter. The important device

internal capacitances that affect the output node (Vo), are indicated. To allow an estimate of

the switching time, using the transient model derived in the ELEC372/672 lectures, we seek

an effective load CL that we can place on the output of the first inverter, to represent the

device internal capacitances and wiring capacitance shown. These capacitances are:

Capacitor Equation Representing

Cgdon 2 CGDO Wn Gate drain overlap

Cgdop 2 CGDO Wp Gate drain overlap

Cgson CGSO Wn Gate source overlap

Cgsop CGSO Wp Gate source overlap

Cdb1 Keqn(ADnCJ + PDnCJSW) Drain body (substrate)

Cdb2 Keqp(ADpCJ + PDpCJSW) Drain body (substrate)

Cg3 Co WnLn Total gate capacitance

Cg4 Co WpLp Total gate capacitance

CW Assume to be 1 femto Farad Interconnect capacitance

CL Combine the above

Integrated Circuit Design Assignment - 8

CGDO, ADn, ADp, CJ, CJSW are SPICE parameters which should be found from the SPICE

netlist. W and L are device width and length; Co is the gate oxide capacitance per unit area.

Keq is a factor that takes account of the voltage dependence of Cdb; it is related to the

capacitance of the depletion region associated with the drain/substrate junction. Junction

depletion capacitance can be written as:

( ) 1

2

−−

+

= abi

DA

DAs

j VVNN

NNq

AC

or 5.0

1

−

=

bi

a

jo

j

V

V

C

C (A2.1)

NA, ND are the average doping levels of drain and substrate regions; Va is the voltage across

the junction and Vbi is the built-in voltage of the junction:

=

2

ln025.0

i

DA

bi

n

NN

V where ni is the intrinsic carrier concentration = 1.5 x 1016 m-3

The non-linear capacitance given by Eqn. A2.1 can be conveniently written as a linear

capacitance Ceq such that for a given voltage swing, the same amount of charge is switched.

We arrive at:

5.05.05.0

5.0)( LbiHbiLH

bi

eq VVVVVV

V

K +−+

−

=

where VH and VL represent the voltage swing of interest and Ceq = KeqCjo

(Note that to compare with the theory developed during the lectures, you would want to take

90% and 10% levels.)

Note that there are a number of approximations made in estimating load capacitance in this

way. The SPICE simulation of course, uses much more accurate models for the capacitances.

You should consider this when trying to compare the theoretical and simulated values of fall

time. Refer to textbooks for further information.

OBTAINING CADENCE SPICE PARAMETERS

Integrated Circuit Design Assignment - 9

The final netlist which is used in the simulations can be obtained by selecting the following in

the Affirma Analog circuit Environment form.

Simulation -> Netlist -> Create Final

To save the file select File -> Save As

Save the file to “~/temp” (overwrite any existing file).

To print the file type “lpr –Peetc ~/temp” from the xTerm window.

Some of the parameters – which are required to compute the rise/fall time – are not displayed.

The parameters which are needed are as follows:

Parameter Definition NMOS PMOS

Vto (V) Threshold voltage 0.9 -0.9

*Nsub (cm-3) Substrate doping concentration 1.39x1015 9.1x1015

*NA , ND (cm

-3) Drain/source doping concentration 1x1021 1x1021

Cj (F/m2) Zero bias bulk junction bottom

capacitance per m2 of junction area

6.9E-5 3.1E-4

Cjsw (F/m) Zero bias bulk junction sidewall

capacitance per m of junction perimeter

3.43E-10 3.67E-10

Mj Bulk junction bottom grading coefficient 0.5 0.5

Cgbo (F/m) Gate to bulk overlap capacitance 5.57E-10 5.57E-10

ld (m) Lateral diffusion 0.22E-6 0.35E-6

tox (m) Gate oxide thickness 40.3E-9 42.46E-9

Kp (A/V2) Transconductance parameter 51.7E-6 19.14E-6

PS=PD (m) Source perimeter 18E-6 18E-6

AS=AD (m2) 17.5E-12 19E-12

Table 2 – Parameters obtained from Cadence

CGDO, CGSO (F/m) = εo εoxld/tox

(εo = 8.85 x 10-12 F/m; εox = 3.9)

* need to put into SI units!

Integrated Circuit Design Assignment - 10

A3: How to compute the dynamic, average power consumption

For a switching period, T (that is, frequency 1/T), average power consumption is defined as

( ) ( )dtti

T

V

dttp

T

P

T

DD

DD

T

av == 00

1

(A3.1)

where iDD is the current drawn from the supply, VDD. In HSPICE, you can use the command

.MEASURE TRAN AVG

to perform the calculation.

Alternatively, the current delivered by the power supply can be found using the circuit shown

below.

Figure A3.1: Circuit used to measure the power

The zero value voltage source is placed in the lead where the current is required to be found.

The ‘meter’ circuit takes this current, multiplies it by some factor K, and uses this scaled

current to charge the capacitor, C. Now we call the voltage across the capacitor Pav and so

DD

av ki

dt

dP

C = or =

T

DDav dttiC

k

P

0

)( (A3.2)

assuming that Pav = 0 at t = 0. If we equate equations A3.1 and A3.2, and we make

k/C = VDD/T, then the voltage across the capacitor gives us the average power dissipation.

We have calibrated the meter.

(Note that the resistor assists in DC convergence and we need to ensure that RC is much

greater than the period of the signals we are investigating. A value of R = 100M should

satisfy this requirement).

To create the circuit of Fig. A3.1, in the schematic cell view, follow the procedure:

Integrated Circuit Design Assignment - 11

1. Select ‘Create->instance’ from the schematic cell view. Select the library

‘analogLib’, the component ‘vdc’, and the cell view ‘symbol’ component.

2. Edit the properties of the voltage source. Set the ‘DC voltage’ to ‘0V’ and the

‘instance Name’ to ‘VREF’

3. Place the voltage source between the power supply and the circuit to be measured.

4. ‘add->instance’. Select the library ‘analogLib’, the component ‘cccs’, and the cell

view ‘symbol’. Place the component in the schematic cell view.

5. ‘add->instance’. Select the library ‘analogLib’, the component ‘res’ and the cell

view ‘symbol’. Place the component in the schematic cell view. Edit it’s properties –

change it’s resistance to ‘100M’

6. ‘add->instance’. Select the library ‘analogLib’, the component ‘cap’ and the cell

view ‘symbol’. Place the component in the schematic cell view. Edit its properties –

change its capacitance to ‘1pF’

7. Edit the properties of the current source. Set the ‘Name of the voltage source’ to

‘VREF’. Set the value of the ‘current gain’ to be equal to VDDC/T where ‘T’ is the

period of the clock pulse, ‘VDD’ is the supply voltage and ‘C’ is the value of the

capacitor.

学霸联盟

ELEC 372 / 472: Integrated Circuit Design Assignment 3

Objective

To understand fundamental concepts underlying CMOS gate speed and power

performance, as covered in ELEC 372/472, in the context of design. To design, verify and

investigate CMOS standard cells conforming to the specified design rules using a

professional, integrated circuit design package, named Cadence.

For guidance, a 15 credit module unit is meant to occupy 150 hours in total (including

both private study and contact hours). You should aim to spend about 3-4 hours per week at

the terminals. The remainder of the time will be taken up with background reading and

research.

KEEP A LOG BOOK OF YOUR PROGRESS.

EFFECTIVE TIME MANAGEMENT IS A KEY SKILL THAT APPLIES TO

ALL PROFESSIONS AND WORKING SITUATIONS.

SO IF YOU GET STUCK, ASK – DO NOT WASTE TIME – STAY FOCUSED

Any queries email below.

Dr. K. Hoettges: k.hoettges@liverpool.ac.uk

Integrated Circuit Design Assignment - 2

Section 1 - Design another 2 input NAND gate (Total marks 30)

Design another two input NAND gate with a capacitive load, CL (You can reuse your code

from assignment 1 do calculate this or appendix A2). The NMOS devices should have a

width of 6um and a length of 3um. The width of the PMOS devices should be equal to the

number assigned to you and length = 3m. The value of CL should reflect the widths of the

NMOS and PMOS devices. Investigate the rise/fall times when the width of both PMOS’s

and also the widths of each NMOS device are varied. Repeat the above and adjust the value

of CL to compensate for the increased widths of the new transistors.

In your report:

Record and comment and explain your results (refer to lecture notes or literature!)

In assignment 1 we model an inverter not a NAND gate, discuss why we can use this to

get an adequate value for CL?

Section 2 - Investigate the power dissipation of the loaded CMOS inverter (refer

to A3). (Total marks 30)

• Using your ‘matched’ value of Wp, employ the ‘power meter’ circuit of appendix 3,

and plot the power dissipation over 5 or more cycles (rise and fall times) of the input

signal. Plot input and output voltage waveforms; drain current of p-MOST and n-

MOST and power dissipation of the DUT on the same page but as separate traces. (10

marks)

• Devise a simulation that allows separation of dynamic power dissipation and short

circuit current power dissipation. Comment on the relative magnitudes of the two

components. Repeat the simulation at a lower frequency and compare the results to

those of the higher frequency. Change the width of the p-MOST to be the same as in

assigned to you in assignment 3 (Look on Vital) and analyse the dynamic and short-

circuit current power.

▪ Quote power consumption in both ‘watts’ and as ‘ energy per transition’.

▪ Check that the values you are getting are sensible. (20 marks)

In your report:

Record and comment and explain your results (refer to lecture notes or literature!)

Explain how the power meter circuit works.

Integrated Circuit Design Assignment - 3

Section 3 - Design a clocked SR Flip Flop and fully test by simulation (Total marks

40)

To design the clocked SR flip flop you should link together the circuits you have already

designed in the previous sections – (Keeping your assigned gate width – marks will be

deducted if this is not the case-). You can place your previous cell layouts in your new layout

by using create/instance. Only add the interconnects to connect the cells together.

Test the circuit with Spectre and then join together your original layout cell views to create a

new complete layout view. You should then and run the DRC am LVS to ensure there are no

errors.

In your report:

Include a printout of the simulation results, the cell views , LVS and DRC and layout in

your report. Comment and explain on your results.

Report:

Please write a report covering all the main design steps and considerations and theory.

Please explain your results – Just stating what happens is insufficient. Use and explain

suitable truth tables for testing. Add screen grabs of schematic, layout and simulation

results where suitable. Remember that only a completed LVS and DRC validate your

layout.

Integrated Circuit Design Assignment - 4

Appendix 1: DRC rules

Design layer rules 1.5um

Drawn layer 1: Active area

1.1 Min. width 1.5

1.2 Min. spacing 2

1.3 Min. spacing to scribe 25

Drawn layer 2 : Pwell

2.1 Min. width 4.0

2.2 Min. spacing 14.0

2.3 Pwell to P+ Active area 3.0

2.4 Nwell to N+ Active area 3.0

2.5 Pwell enclosure of N+ (P+) Active area 3

2.6 N-field enclosure of P-well 3

Drawn layer 4: Polysilicon

4.1 Min. width 1.5

4.2 Min. spacing 2.0

4.3 Min. spacing of gate field from active area edge 1.0

4.4 Min. gatepoly extension over active area edge 1.5

4.5 Min. width of source/drain region 2

4.6 Min. spacing to scribe 25

Drawn layers 5/6: P+/N+ diffusion

5.1 Min. width 2.5

5.2 Min. spacing 1.5

5.3 D/S terminal overlap of active area 1

5.4 Overlap of N+/P+ for butt contacts 0.5

5.5 Overlap of S/D for gated diode 0.5

5.6 P+ spacing to unrelated N+Active Area 1.5

5.7 N+ spacing to unrelated P+Active Area 1.5

Drawn layer 7: Contacts

7.1 Min/Max. width 2.0x2.0

7.2 Min. Spacing 2.0

7.3 Min. spacing of gate poly contact to active area edge 2.0

7.4 Min spacing of active area contact to gate poly 1.5

7.5 Min. enclosure by Active area 1.0

7.6 Min. enclosure by gate poly 1.0

7.7 Min. spacing to scribe 25

Drawn layer 8: Metal 1

Integrated Circuit Design Assignment - 5

8.1 Min. width 3

8.2 Min. spacing 2.0

8.3 Min. overlap of contact 1.0

8.4 Min. spacing to scribe 25

Drawn layer 9: Via

9.1 Min./Max. width 2.0

9.2 Min. spacing 2.0

9.3 Min. enclosure of metal 1/metal 2 1.0

9.4 Min. spacing to active area edge 1.5

9.5 Min. spacing to gate poly edge 1.5

9.6 Min. spacing to contact 1.5

9.7 Stacking via over contact is not permitted -

9.8 Min. spacing to scribe 25

Drawn layer 10: Metal 2

10.1 Min. width 3.0

10.2 Min. spacing 2.0

10.3 Min. overlap of via 1.0

10.4 Min. spacing to scribe 25

2um (DRC 7.3)

1um1um

2.0um (DRC 7.1)

1um (DRC 4.3)

2um 1.5um

2um (DRC 4.2)

(DRC 4.5) (DRC 4.1)

1.5um (DRC 4.4)

(DRC 7.5) (DRC 7.4)

= contact

= polysilicon

= N+ diffusion

= active area

Integrated Circuit Design Assignment - 6

LSW window

Selected layer for drawing

Text dg Text layer - cosmetic

M1Q dg metal 1

M2Q dg metal 2

AAQ dg active area

PLQ dg polysilicon

PWQ dg P well

NFQ dg N-field

PPQ dg P+ doping

NNQ dg N+ doping

V1Q dg via

CTQ dg contact

OSC dg outer schematic layer – cosmetic layer

ISC dg inner schematic layer – cosmetic layer

M1Q pn metal1 pin

M2Q pn metal2 pin

DEM pn DEM pin layer – used for “subvdd!”

Integrated Circuit Design Assignment - 7

A2: How to estimate the load capacitance, CL

CGDOn

CGDOp

CGSOp

CGSOn

CGp

CGn

Cdbp

Cdbn

Vin

Vout Vout2

CW

VDD

Figure A2.1 – Unity fan-out inverter

The figure shows a CMOS inverter loaded with another inverter. The important device

internal capacitances that affect the output node (Vo), are indicated. To allow an estimate of

the switching time, using the transient model derived in the ELEC372/672 lectures, we seek

an effective load CL that we can place on the output of the first inverter, to represent the

device internal capacitances and wiring capacitance shown. These capacitances are:

Capacitor Equation Representing

Cgdon 2 CGDO Wn Gate drain overlap

Cgdop 2 CGDO Wp Gate drain overlap

Cgson CGSO Wn Gate source overlap

Cgsop CGSO Wp Gate source overlap

Cdb1 Keqn(ADnCJ + PDnCJSW) Drain body (substrate)

Cdb2 Keqp(ADpCJ + PDpCJSW) Drain body (substrate)

Cg3 Co WnLn Total gate capacitance

Cg4 Co WpLp Total gate capacitance

CW Assume to be 1 femto Farad Interconnect capacitance

CL Combine the above

Integrated Circuit Design Assignment - 8

CGDO, ADn, ADp, CJ, CJSW are SPICE parameters which should be found from the SPICE

netlist. W and L are device width and length; Co is the gate oxide capacitance per unit area.

Keq is a factor that takes account of the voltage dependence of Cdb; it is related to the

capacitance of the depletion region associated with the drain/substrate junction. Junction

depletion capacitance can be written as:

( ) 1

2

−−

+

= abi

DA

DAs

j VVNN

NNq

AC

or 5.0

1

−

=

bi

a

jo

j

V

V

C

C (A2.1)

NA, ND are the average doping levels of drain and substrate regions; Va is the voltage across

the junction and Vbi is the built-in voltage of the junction:

=

2

ln025.0

i

DA

bi

n

NN

V where ni is the intrinsic carrier concentration = 1.5 x 1016 m-3

The non-linear capacitance given by Eqn. A2.1 can be conveniently written as a linear

capacitance Ceq such that for a given voltage swing, the same amount of charge is switched.

We arrive at:

5.05.05.0

5.0)( LbiHbiLH

bi

eq VVVVVV

V

K +−+

−

=

where VH and VL represent the voltage swing of interest and Ceq = KeqCjo

(Note that to compare with the theory developed during the lectures, you would want to take

90% and 10% levels.)

Note that there are a number of approximations made in estimating load capacitance in this

way. The SPICE simulation of course, uses much more accurate models for the capacitances.

You should consider this when trying to compare the theoretical and simulated values of fall

time. Refer to textbooks for further information.

OBTAINING CADENCE SPICE PARAMETERS

Integrated Circuit Design Assignment - 9

The final netlist which is used in the simulations can be obtained by selecting the following in

the Affirma Analog circuit Environment form.

Simulation -> Netlist -> Create Final

To save the file select File -> Save As

Save the file to “~/temp” (overwrite any existing file).

To print the file type “lpr –Peetc ~/temp” from the xTerm window.

Some of the parameters – which are required to compute the rise/fall time – are not displayed.

The parameters which are needed are as follows:

Parameter Definition NMOS PMOS

Vto (V) Threshold voltage 0.9 -0.9

*Nsub (cm-3) Substrate doping concentration 1.39x1015 9.1x1015

*NA , ND (cm

-3) Drain/source doping concentration 1x1021 1x1021

Cj (F/m2) Zero bias bulk junction bottom

capacitance per m2 of junction area

6.9E-5 3.1E-4

Cjsw (F/m) Zero bias bulk junction sidewall

capacitance per m of junction perimeter

3.43E-10 3.67E-10

Mj Bulk junction bottom grading coefficient 0.5 0.5

Cgbo (F/m) Gate to bulk overlap capacitance 5.57E-10 5.57E-10

ld (m) Lateral diffusion 0.22E-6 0.35E-6

tox (m) Gate oxide thickness 40.3E-9 42.46E-9

Kp (A/V2) Transconductance parameter 51.7E-6 19.14E-6

PS=PD (m) Source perimeter 18E-6 18E-6

AS=AD (m2) 17.5E-12 19E-12

Table 2 – Parameters obtained from Cadence

CGDO, CGSO (F/m) = εo εoxld/tox

(εo = 8.85 x 10-12 F/m; εox = 3.9)

* need to put into SI units!

Integrated Circuit Design Assignment - 10

A3: How to compute the dynamic, average power consumption

For a switching period, T (that is, frequency 1/T), average power consumption is defined as

( ) ( )dtti

T

V

dttp

T

P

T

DD

DD

T

av == 00

1

(A3.1)

where iDD is the current drawn from the supply, VDD. In HSPICE, you can use the command

.MEASURE TRAN AVG

to perform the calculation.

Alternatively, the current delivered by the power supply can be found using the circuit shown

below.

Figure A3.1: Circuit used to measure the power

The zero value voltage source is placed in the lead where the current is required to be found.

The ‘meter’ circuit takes this current, multiplies it by some factor K, and uses this scaled

current to charge the capacitor, C. Now we call the voltage across the capacitor Pav and so

DD

av ki

dt

dP

C = or =

T

DDav dttiC

k

P

0

)( (A3.2)

assuming that Pav = 0 at t = 0. If we equate equations A3.1 and A3.2, and we make

k/C = VDD/T, then the voltage across the capacitor gives us the average power dissipation.

We have calibrated the meter.

(Note that the resistor assists in DC convergence and we need to ensure that RC is much

greater than the period of the signals we are investigating. A value of R = 100M should

satisfy this requirement).

To create the circuit of Fig. A3.1, in the schematic cell view, follow the procedure:

Integrated Circuit Design Assignment - 11

1. Select ‘Create->instance’ from the schematic cell view. Select the library

‘analogLib’, the component ‘vdc’, and the cell view ‘symbol’ component.

2. Edit the properties of the voltage source. Set the ‘DC voltage’ to ‘0V’ and the

‘instance Name’ to ‘VREF’

3. Place the voltage source between the power supply and the circuit to be measured.

4. ‘add->instance’. Select the library ‘analogLib’, the component ‘cccs’, and the cell

view ‘symbol’. Place the component in the schematic cell view.

5. ‘add->instance’. Select the library ‘analogLib’, the component ‘res’ and the cell

view ‘symbol’. Place the component in the schematic cell view. Edit it’s properties –

change it’s resistance to ‘100M’

6. ‘add->instance’. Select the library ‘analogLib’, the component ‘cap’ and the cell

view ‘symbol’. Place the component in the schematic cell view. Edit its properties –

change its capacitance to ‘1pF’

7. Edit the properties of the current source. Set the ‘Name of the voltage source’ to

‘VREF’. Set the value of the ‘current gain’ to be equal to VDDC/T where ‘T’ is the

period of the clock pulse, ‘VDD’ is the supply voltage and ‘C’ is the value of the

capacitor.

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