SCHOOL OF ENGINEERING
ANALOGUE CIRCUIT DESIGN
ELEE11045
Exam Diet: April/May 2020 Duration: 48 hours Expected workload: Two Hours plus upload
Exam starts: 13:00 on 25/05/2020 Exam ends: 13:00 on 27/05/2020 All times are BST (UTC+1)
Before commencing work, please read the academic, formatting, scanning and uploading guidance.
Examination information
• This paper consists of TWO sections.
• Candidates should attempt THREE questions, chosen as follows:
• Section A: ONE question. Attempt the whole section.
• Section B: Answer TWO out of the THREE questions. Only TWO out of three questions will be
marked. Candidates must indicate which two questions are to be marked if three questions have been
answered. If no indication is provided, the examiner will mark the FIRST TWO questions answered.
Specific instructions
• Students should assume reasonable values for any data not given in a question, or not available on a
datasheet, and should make any such assumption clear on their answer sheets.
• Students in any doubt as to the interpretation of the wording of a question, should make their own decision,
and should state it clearly on their answer sheet.
• Write concise, complete answers. If a length limit is given, stay within it. Produce equations and diagrams to a
good handdrawn standard.
• This is an open book exam. This means you can freely access any printed or online materials to aid you in
your answers. Online materials can include text, images, videos and data. You may NOT engage in
interactions or discussions relating to the exam questions or examined subject matter in any form. Sharing
the answers to this exam in any way, by any means and in any form is STRICTLY NOT allowed.
• Use only a standard calculator. Do not use computerbased spreadsheets, mathematical solvers, simulation
tools, graphing calculators or any other tool which is interactive in nature, such as online mathematical
equation solvers.
Technical instructions (For full details see the formatting guidance and how to upload your exam to learn)
• Write in dark blue or black ink on white or lightcoloured A4 paper, or the nearest equivalent size; unlined,
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instructions.
• Name your file with the course code and your examination number, e.g. ENGI00000B123456.pdf
• Check your file carefully then upload it in the ONLINE EXAM area for this course on LEARN.
• If you require technical support, contact Exams.Eng@ed.ac.uk
Special Items
None.
Convenor of Board of Examiners: Dr A Hamilton
External Examiner: Professor R Stewart
ELEE11045 Analogue Circuit Design – May 2020
SECTION A
Question A1
a) The standard expression for a normalised, first order, low pass filter
section is: () = + 1
and for a normalised second order low pass section is: () = ! + + 1
Use these equations as the starting point to obtain:
(i) The standard expressions for denormalised (wc ≠ 1) first and
second order low pass filter sections.
(ii) The standard expressions for denormalised first and second
order high pass sections. (4)
b) Figure A1 shows the circuit diagram for a Schmitt trigger regenerative
comparator where the op amp has a dual rail supply and has limits of
±VA.
(i) Derive or write down the expression for V1 in figure A1.
(ii) Derive expressions for the comparator switching threshold
voltage when Vi is both increasing (Vi1) and decreasing (Vi2)
and hence derive the hysteresis width for the comparator input.
Assume that the limits of the linear region of the comparator
when operated open loop extend from the amplifier differential
input V – V+ = –Va to V – V+ = +Va. (6)
c) GmC filters are extremely useful structures for integrated circuit
applications.
(i) Draw a singleended GmC integrator.
(ii) Write down the transfer function of the integrator and calculate
the transconductance value needed for an integrator that has a
unitygain frequency of 20 MHz, assuming a 2 pF integrating
capacitor.
(iii) Draw the differential GmC integrator structure that is less
susceptible to parasitic capacitance, and state its
disadvantage? (5)
ELEE11045 Analogue Circuit Design – May 2020
d) Large commonmode (CM) signals are a major problem for high
precision analogue circuits.
(i) Define the common mode rejection ratio (CMRR) of an
amplifier.
(ii) Draw a 5transistor operational transconductance amplifier
(OTA). In the same circuit sketch show how a sixth transistor
and a current source can be used to bias the tail current.
(iii) Explain the two main reasons that can lead to low CMRR in
this OTA.
(5)
Figure A1

+ R1
R2
Vo
Vi
V1
Vref
ELEE11045 Analogue Circuit Design – May 2020
SECTION B
Question B1
a) A sine wave phase shift oscillator circuit is shown in figure B1 where
the positions of the Rs and Cs are exchanged compared to the CR
stages in the similar circuit given in the lecture materials. Apply the
Barkhausen Criterion to the circuit and derive:
(i) An expression containing R and C for the oscillation frequency
of the circuit.
(ii) The magnitude of the gain required from the inverting amplifier
to ensure oscillation.
(10)
b) The phase shift oscillator is commonly constructed using four op amps
as shown in figure B1 because it is an efficient use of a quad amplifier
package. In this form it can have two outputs labelled as VoA and VoB
in figure B1.
(i) Derive the amplitude and phase relationships between VoA
and VoB at oscillation, and suggest how the two outputs might
be named or described.
(ii) How should the circuit be modified if the amplitude of both
outputs VoA and VoB is required to be the same (without
requiring additional opamps)? Give numerical values for the
appropriate circuit parameters.
(iii) What condition must be imposed on the inverting amplifier
stage if the circuit is to oscillate at the frequency derived in
part a(i)?
(10)
Figure B1
+

R
C
+

R

+
R
C
Rf
VoBC
+

R
VoA
C
Ri
ELEE11045 Analogue Circuit Design – May 2020
Question B2
a) The transfer function of the KerwinHuelsmanNewcomb (KHN)
secondorder section shown in Figure B2a is:
(i) Give the dc gain, the Q and the cutoff frequency, w0, of this
section in terms of the values of the components in the transfer
function.
(ii) Derive the sensitivities of w0 and Q to each of the passive
components that appear in the transfer function.
(iii) The filter is to be used in an application where both w0 and Q
must not be permitted to deviate more than 1% from nominal,
but where temperature variation and ageing can cause the
passive component values to change by up to +0.6%.
Demonstrate whether the KHN circuit given will be suitable for
the application or not.
(10)
b) A phase locked loop (PLL) is constructed using an XOR gate (output =
0 V or 5 V), and a voltagecontrolled oscillator (VCO) with a free
running frequency of 5 MHz and an output that changes by 10 kHz for
every 1 V change in input voltage.
(i) Draw the simplest possible block diagram of this PLL and
sketch its openloop response labelling key points on your
sketch carefully.
(ii) If your PLL was locked to an input signal of 5.02 MHz for a
long time and then, at time t = 0 the frequency of the input
signal suddenly changed to 5.035 MHz, sketch the waveform
that would appear at the VCO input. Give values for any time
constants.
A SallenKey circuit is shown in figure B2b and it has the transfer
function:
"#$%& = 1!!! + ( + 1) + 1
(iii) Replace the resistors in this circuit with the simplest possible
switchedcapacitor equivalent and a clock frequency FC.
(iv) Derive the ratio of the two new capacitors you have used for
this purpose?
(v) If the bandwidth of the filter is 5 kHz, what condition must be
applied to FC?
(10)
123
2
22
2
2121 ++
=
sCRsCCRRV
V
in
out
ELEE11045 Analogue Circuit Design – May 2020
Figure B2a
Figure B2b
ELEE11045 Analogue Circuit Design – May 2020
Question B3
a) You require to obtain a very high gain for a differential signal% = ' − !. However, due to some practical reasons, the signals from
the two sources have to be individually amplified by two lowgain (A1)
singleended amplifiers before sending the signal to a highgain (A2
=100) differential amplifier as shown in Fig B3a.
(i) Write down the algebraic form of total input referred noise &,%.
(ii) The input referred noise of the lowgain amplifiers is&'(= 3 ) each and that of the differential amplifier is&!(= 10 ). If the total input referred noise has to be
restricted to within 1.5 times of &', what is the minimum A1
necessary? (6)
b) Consider the circuit shown in fig B3b. The sinusoidal input at 3 kHz
has a magnitude of 0.64 V rms. Calculate the ratio of signal and noise
at the output (") in terms of R1, R2 and C. Assume R1 = R2 = 200 Ω,
C = 1 pF, Boltzmann constant = 1.38 × 10)!* J K1 and temperature
is 27 °C to determine the magnitude of signal to noise ratio (SNR =10 log +!"#+$%"!&) in dB. (7)
c) (i) When a NMOS device is in saturation, prove that the transistor
transconductance , is proportional to √ for a given /.
Assume = 0.
(ii) Draw a supply independent current reference circuit that is not
affected by ./ shift of transistors.
(iii) Show how you can use this circuit to create a supply
independent voltage source. (7)
Figure B3a
Figure B3b
+

V1
V2
Vo
A1
A2
END OF PAPER
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