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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019 5367
Josephson Junction Field-Effect Transistors for
Boolean Logic Cryogenic Applications
Feng Wen , Javad Shabani, and Emanuel Tutuc , Senior Member, IEEE
Abstract— Josephson junction FETs (JJ-FETs) share
design similarities with MOSFETs, except for the
source/drain contacts being replaced by superconductors.
Similarly, the super current due to proximity effect is
tunable by the gate voltage. In light of recent advances in
novel materials and fabrication techniques, we examine
here the feasibility of JJ-FET-based Boolean logic and
memory elements for cryogenic computing. Using a 2-D
ballistic transport JJ-FET model, we implement circuit-level
simulations for JJ-FET logic gates and discuss criteria for
realizing signal restoration, as well as fan-out. We show
that the JJ-FET is a promising candidate for very low-
power, clocked voltage-level dynamic logic at cryogenic
temperatures.
Index Terms— Ballistic transport, Josephson junction
(JJ), superconducting logic device.
I. INTRODUCTION
REDUCING temperature (T ) improves several key devicemetrics of the MOSFETs. Examples include enhanced
channel mobility and reduced subthreshold swing (SS), which
scales linearly with T as SS = 2.3 (kT/e)/decade; k is
Boltzmann’s constant and e is the electron charge. Channel
injection efficiency can be improved in the absence of phonon
scattering [1], and the resistance of metal interconnects is
expected to decrease at lower temperatures. It is, therefore,
important to investigate under what conditions cryogenic com-
puting provides a net benefit in terms of dissipated energy
per switching operation and whether other devices can offer
a benefit in performance at reduced temperatures. For a given
technology with supply voltage VDD, the energy dissipated
per switching operation is CVDD2/2, where C represents the
device capacitance. Assuming VDD(T ) can be reduced at lower
T , by requiring that the total energy dissipated per switching
operation, including the cooling cost, does not exceed the room
Manuscript received September 13, 2019; accepted October 22, 2019.
Date of current version November 27, 2019. This work was supported
in part by the National Science Foundation under Grant DMR-1507654
and in part by Intel Corporation. The review of this article was arranged
by Editor S. Hong. (Corresponding author: Emanuel Tutuc.)
F. Wen and E. Tutuc are with the Microelectronics Research Center,
Department of Electrical and Computer Engineering, The University of
Texas at Austin, Austin, TX 78758 USA (e-mail: wenfeng@utexas.edu;
etutuc@mer.utexas.edu).
J. Shabani is with the Center for Quantum Phenomena, Department of
Physics, New York University, New York, NY 10003 USA.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2019.2951634
temperature value, we arrive at the following energy balance
equation:
CVDD(300 K)2
2
= CVDD(T )
2
2
+ 300 K−T
T
· CVDD(T )
2
2
. (1)
The second term on the right-hand side (RHS) of (1) represents
the cooling cost at the ideal Carnot efficiency, corresponding
to reservoir temperatures of 300 K and T . Equation (1) leads
to the following simple scaling law for the operating voltage to
break even in the ideal cooling limit:
VDD(T ) = VDD(300 K)
√
T
300 K
. (2)
For example, a VDD value of 0.7 V at room temperature will
translate to a break-even value of 83 mV at 4.2 K, the liquid
He boiling point, which is further reduced to ∼26 mV if
one factors in realistic cooling efficiencies of 5%–10% [2].
The gate delay associated with load and parasitic capacitance
being charged/discharged will scale with reducing VDD, while
the transit time delay of channel being switched may not
scale down proportionally because of low Fermi velocity at
low carrier concentration and reduced thermal excitation of
carriers [3]. While the above arguments contain a number of
simplifications, they clearly indicate that cryogenic computing
using CMOS concepts is subject to significant constraints if a
net benefit is expected over room-temperature operation with
cooling cost factored in. It is, therefore, highly relevant to
examine if other devices operating at or below the break-even
VDD value may be used for cryogenic computing applications.
Josephson-logic devices can operate at VDD values in the
millivolt range utilizing superconductivity [4], the most spec-
tacular material property that emerges at low temperatures as
a result of electrons forming Cooper pairs. The devices are
based on the Josephson junction (JJ), a two-terminal device
consisting of two superconductor contacts separated by a
weak link, allowing current flow without dissipation (super-
current) due to proximity effect. The feasibility of JJ-FET,
a three-terminal device with gate-tunable supercurrent, for
logic operation was discussed decades ago [5], [6]. The JJ-FET
design is similar to a MOSFET except that the source and
drain are superconducting at cryogenic temperatures, and the
channel length is sufficiently short to allow coherent transport
of Cooper pairs through the channel. JJ-FETs have been
experimentally demonstrated on various material platforms,
including Si, Ge, and III–V compounds [7]–[9]. Advances in
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5368 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019
Fig. 1. Schematic of a JJ-FET consisting of superconducting source
and drain, metal gate, oxide, semiconductor channel, and insulating
substrate. The length scales L, ξ0, and λ are indicated. The scatter-
ing or destruction of Cooper pairs will occur if L is greater than λ or ξ0,
respectively, as shown in the figure. Arrows: Cooper pairs or electrons
motion.
fabrication techniques and emerging channel materials, such
as nanowires, III–V quantum-wells, and graphene, as well as
the development of transparent semiconductor/superconductor
interfaces render the topic of JJ-FETs timely [10]–[13].
In this article, we address the feasibility of JJ-FETs for digi-
tal applications. We employ a JJ-FET device model that allows
gate-controlled ballistic and coherent transport of Cooper
pairs through the channel to examine the criteria for signal
restoration of several logic gates. We present the results of
transient analysis of JJ-FET logic gates, evaluate the impact
of fan-out on device behavior, and discuss various design
considerations.
II. JJ-FET DEVICE MODEL
We begin by introducing a device model for the JJ-FET.
The device, schematically shown in Fig. 1, has the following
key length scales: the channel length (L), the Cooper pair
coherence length (ξ0), and Cooper pair mean free path (λ).
Depending on the interplay between L, ξ0, and λ, the JJ can
operate in either short or long ballistic or diffusive regimes.
The JJ is short if L < ξ0 or long if L > ξ0. The Cooper pair
transport is ballistic if L < λ or diffusive if L > λ.
Here, we consider the case of a short ballistic JJ device,
which satisfies the Ambegaokar–Baratoff formula [14]
V0 = IC · RN = pi (3)
where IC is the critical current, RN is the normal resistance
of the JJ, and is half the superconductor gap voltage. The
conductance of a 2-D ballistic transport layer, divided by the
average velocity along the channel direction, is
gn = W ·2e
2
h
· 2
pi
· √2pin (4)
where W is the device width, h is the Planck constant, and
n is the carrier density. The carrier density can be related to
Fig. 2. Calculated I–V characteristics for JJ-FETs with W = 1 µm,
effective SiO2 oxide thickness of 1 nm (CG = 3.45 µF/cm2) using(a) Nb and (b) Al contacts. The VG −VT values indicated in the figure are
changed in (a) 1- and (b) 0.5-mV increments.
gate capacitance (CG) and gate voltage (VG) via n = CG(VG−
VT)/e; VT is the threshold voltage. Using (3) and (4)
IC = gn·V0 = 2V 0W ·2eh ·
√
2eCG(VG − VT)
pi
. (5)
It is instructive to introduce an equivalent conductance for the
IC dependence on VG as
β = d IC
dVG
= V0 dgndVG = V0W ·
2e
h
·
√
2eCG
pi(VG − VT) . (6)
If we assume the device is in the overdamped limit, where
I–V characteristics are nonhysteretic [15], [16], the static I–V
characteristics are relatively simple
VDS = RN
√
I 2DS − I 2C (IDS > IC)
VDS = 0 (IDS < IC) (7)
where VDS is the voltage drop across the drain and source con-
tacts and IDS is the drain current. Because Nb and Al are two
commonly used superconductors [17], [18], we consider here
the cases where the source/drains consist of either Nb or Al
with values of 1.5 or 0.22 mV, respectively [19]. Fig. 2
shows the static I–V characteristics of JJ-FETs with the two
metal contacts.
A critical question for a logic gate is if the output voltage
is sufficiently large to switch the next stage. To address this
question let us assume the output of one JJ-FET is directly
driving the gate of a second JJ-FET, whose IC value, in turn,
needs to be sufficiently modulated for a switch. Equation (7)
indicates that VDS will be of the order of V0 if IDS is
comparable to IC [4]. The relative change in IC corresponding
to a gate swing of V0 is [20]
αR = βV0IC =
V0
2(VG − VT) . (8)
To achieve signal restoration αR ∼ 1, hence VG − VT needs
to be comparable to V0. This is an intrinsic requirement of
JJ-FET logic gate, independent of device scaling and geometry.
Fig. 3 shows the plots of αR against VG − VT for both
Nb- and Al-contact JJ-FETs.
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WEN et al.: JJ-FETs FOR BOOLEAN LOGIC CRYOGENIC APPLICATIONS 5369
Fig. 3. Calculated αR versus VG − VT for (a) Nb- and (b) Al-contact
JJ-FET.
Fig. 4. Schematics of JJ-FET (a) inverter, (b) NOR gate, and (c) SRAM.
III. JJ-FET LOGIC GATES
A. Static Analysis
In this section, we consider logic gates based on JJ-FETs.
Fig. 4(a)–(c) shows the schematics of the JJ-FET inverter, NOR
gate, and static random access memory (SRAM), respectively.
A NOR gate is universal and can be the building block for any
combinatorial logic circuit. In this article, we assume all logic
devices are biased with ideal dc current (IBias) sources for
simplicity. The logic gates operate as follows. For a JJ-FET
inverter [see Fig. 4(a)], when the input voltage at the gate
(VIN) is at logic low (VG,Lo), the corresponding IC < IBias
and the JJ-FET is resistive, leading to a finite output voltage
(VOUT). On the other hand, when VIN is at logic high (VG,Hi),
the corresponding IC > IBias, the JJ-FET is superconducting,
and VOUT is zero. Consequently, we have VG,Lo = 0 since
the JJ-FETs are cascaded in logic circuits. Signal restoration
indicates the finite VOUT at VIN = VG,Lo at least equal to
VG,Hi to drive the input of the next stage, i.e., the same input–
output swing. Similarly, in a JJ-FET NOR gate [see Fig. 4(b)],
the sum of IC of the two JJ-FETs is smaller than IBias only
when both inputs are at logic low, leading to a finite VOUT
and zero otherwise. Connecting two JJ-FET inverters back to
back yields an SRAM cell [see Fig. 4(c)], where V1 and V2
will reach a stable state of complementary values.
Next, we design the JJ-FET inverter using the static model
and investigate its performance, ignoring any parasitic capac-
itance and resistance of the JJ-FET itself. Though this model
may be oversimplified, it sheds lights on the dc operating
point, i.e., VT and IBias values will produce the same input–
output swing, namely VG,Hi = VOUT(VG,Lo) = RN(VG,Lo) ·√
(I 2Bias− I 2C(VG,Lo)) and optimal power or speed; the variables
in parentheses denote the VIN values. We can estimate the
Fig. 5. (a) τmin = min(tr + tf) among bias points with their respective
equal input–output swing at each |VT|. (b) Transient analysis result with
minimum τmin using the following set of parameters: Swing of input–
output = 5.9 mV, W = 1 µm, VT = −1.2 mV, and IBias = 15.1 µA. The
superconducting contacts are Nb.
power consumption of the JJ-FET as ∝ IBiasVG,Hi. Hypotheti-
cally, we could have an arbitrarily small swing and thus power
consumption by choosing IBias close to IC(VG,Lo). We could
also have an arbitrarily large swing since RN(VG,Lo) diverges
when VT approaches zero. Hence, for any given swing,
we have a solution to the bias point by appropriately choosing
VT and IBias, albeit with tradeoffs. Therefore, we chose to
design the bias point of the logic gates based on speed.
The rising delay (tr) is not expected to be reduced compared
to that of the traditional counterpart, e.g., an NMOS inverter,
because when VIN switches to low, the JJ-FET becomes
resistive instead of being cut off. Moreover, the JJ-FET draws
additional current to the resistive component, namely the
Josephson current (IJ), effectively further slowing down the
charging speed at the output node. On the other hand, IJ will
assist to discharge the output node when VIN switches to high.
The falling delay (tf) is, therefore, smaller than that of an
NMOS inverter, and more importantly, the superconducting
JJ-FET can fully discharge the output. Fig. 5(a) presents the
plot of minimum total delay τmin as a function of |VT| for an
Nb-contact JJ-FET inverter. The device has the same geometry
as that assumed in Fig. 2 and an output capacitance CL =
10 fF, chosen as fan-out of four plus interconnect capacitance.
For reference, the gate capacitance of a JJ-FET with W =
1 µm and L = 50 nm is 1.7 fF. We note the actual value of CL
is insignificant to demonstrate the logic operation here, since
the characteristics of JJ-FET logic gates using the static I–V
model will not change with CL, except for the delay to scale
linearly. For a fixed VT, a given IBias > IC(VG,Lo) decides
VOUT(VG,Lo) and therefore the output swing. Meanwhile, IBias
cannot exceed IC(VOUT(VG,Lo)) so there is a matched input
swing. Hence, we have multiple solutions of various IBias to
the bias point at each VT. We first determine those quiescent
points, then extract tr and tf for individual point from transient
analysis, and finally obtain τmin at that VT as the minimum of
(tr + t f) among those points. Effectively, the curve in Fig. 5(a)
is the projection of a trace along the contour plot for (tr + t f)
against VT and IBias. We find that τmin reaches a global
minimum at VT ≈ −0.8, where the VIN swing is ≈ 4.
Using this bias point, an example of transient analysis for the
Nb-contact JJ-FET inverter is shown in Fig. 5(b). It is clear
that the falling edge of VOUT is more linear than exponential
compared with the rising edge thanks to IJ, which remains
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5370 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019
Fig. 6. (a) Transient response of the node voltages at the outputs of the
two JJ-FETs in an SRAM cell. (b) Voltage transfer curves indicating the
two stable operation points. The static noise margin is indicated with a
dashed-line box. CL = 1 fF at both outputs. The superconductor contacts
are Nb.
∼ IC and does not linearly decrease with VOUT as the resistive
counterpart. The tr and tf values are 6.4 and 2 ps in this case.
Similarly, a NOR gate can be constructed by simply doubling
IBias since 2IBias < IC(VG,Hi) + IC(VG,Lo).
Applying the same set of parameters for the Nb-contact
JJ-FET inverter in Fig. 5(b), Fig. 6(a) shows the transient
response of the output voltages V1 and V2 for the two JJ-FET
inverters in an SRAM cell. The initial voltage values at the
two outputs are associated with the metastable state (V1 =
V2 ≈ 1.5 mV). In the presence of any disturbance, which is
ubiquitous in an actual circuit, the feedback loop will stabilize
the two inverters to their respective conditions. The final state
is one of the two stable states, where V1 and V2 have opposite
logic values. In this example, the metastable state ends due
to a disturbance at 25 ps and the cell reaches the stable state
where V1 = 5.9 mV and V2 = 0 mV, representing a bit “1”
stored in the cell. Other initial conditions will work as if the
disturbance is already given. Fig. 6(b) presents the voltage
transfer curves of the two JJ-FETs in the same SRAM cell
with the static noise margin indicated in a dashed-line box.
The intersection of the two curves in the middle indicates the
metastable state while the two at the ends represent the stable
states pointed by arrows.
B. Dynamic Analysis
Although we can design the dc operating point of JJ-FET
logic gates with the static model, we have made a critical
assumption that the JJ-FETs are overdamped in the transient
analysis. If a JJ works in the overdamped regime and carries
a current exceeding IC, it is nonhysteretic and will become
superconducting immediately when the current falls below IC.
For an overdamped and resistive JJ-FET, it means the transistor
will become superconducting as soon as VG is increased such
that IC > IDS. However, a JJ or JJ-FET is overdamped only
when the Stewart–McCumber parameter Q = 2pi R2C IC/ 0
is small (Q 4) [15], [16], where R and C are the
resistance and capacitance across the junction, and 0 is the
magnetic flux quantum. On the other hand, a JJ becomes
underdamped if Q is large, which means it remains in the
resistive state even when the junction current is reduced below
IC, leading to I–V hysteresis. The assumption of overdamped
operation becomes questionable if we acknowledge that a
logic device has fan-out, and therefore, has larger C as well
as Q than a single transistor. Moreover, by ignoring the
Josephson inductance LC = /2eIC, the estimation of gate
delay is no longer accurate, as the dominant time constant
of an overdamped JJ-FET is the Josephson time constant
τRL = LC/RN = /(ne). To address these dilemmas, we
implement the resistively and capacitively shunted junction
(RCSJ) model to describe the device. The I–V characteristics
are controlled by the time-dependent variable ϕ(t), which
is the macroscopic phase difference of the superconducting
contacts
IDS(t) = C dVDS(t)dt +
VDS(t)
R
+ ICsinϕ(t)
VDS(t) = 2e ·
dϕ(t)
dt
(9)
where ICsinϕ(t) represents IJ. We assume the load is purely
capacitive and ignore the resistance of the biasing circuitry.
Therefore, a JJ-FET inverter’s device resistance R = RN and
capacitance C = CL+CJ, where CJ is the junction capacitance
assuming gate capacitance splits symmetrically to the source
and drain. The gate-tunable Q for a JJ-FET inverter writes
Qinv = R
2C IC
0/2pi
= pi
3/2V0(CJ + CL)√
2eCG(VIN − VT) (10)
where CJ and CL are normalized to W = 1 µm of the active
JJ-FET. We have CL ∝ CG if the output is driving inputs of
other JJ-FETs, and hence, for a JJ-FET logic inverter, Qinv ∝
(CG/(VG − VT))1/2.
Fig. 7 presents the results of transient analysis for both
Nb- and Al-contact JJ-FET inverters with device parameters
adapted from the static analysis based on VT ≈ −0.8.
Fig. 7(a) and (b) shows the input waveforms for the Nb- and
Al-contact JJ-FET inverters, respectively. Fig. 7(c) and (d)
shows the output waveforms for the Nb- and Al-contact
JJ-FET inverters with CL = 1 fF. Similarly, the output
waveforms for the Nb- and Al-contact JJ-FET inverters with
CL = 5 fF are shown in Fig. 7(e) and (f). The values of
CL in the dynamic analysis section are chosen to represent
the respective operation regime whether hysteresis will latch
the JJ-FET in the resistive state or not. Table I summarizes the
values of Q associated with different CL and zero VIN for both
Nb- and Al-contact JJ-FET inverters. Comparing the output
waveforms to those using the static model, superimposed
oscillations emerge because of the Josephson effect. Similar
to a parallel RLC circuit, the amplitude is attenuated by larger
CL, and the frequency is higher for the Nb-contact device due
to smaller LC. The Nb-contact JJ-FET inverter is significantly
faster than its Al-contact counterpart, e.g., tf = 0.25 and
2.5 ps, respectively, with CL = 1 fF. The difference in
their tf is comparable to that of their τRL . If we compare
Fig. 7(c) and (d) with Fig. 7(e) and (f), a distinct difference
that can be seen is that JJ-FET inverters fail to be reset into the
superconducting states when VIN switches from zero to high
when CL is increased from 1 to 5 fF. Consequently, the finite
Q must be accounted for when designing JJ-FET logic gates
to avoid an undefined VOUT. In the simulation, we find
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WEN et al.: JJ-FETs FOR BOOLEAN LOGIC CRYOGENIC APPLICATIONS 5371
Fig. 7. Square waveforms of VIN for (a) Nb-contact JJ-FET inverter(0 ∼ 6 mV) and (b) Al-contact JJ-FET inverter (0 ∼ 1.1 mV) with a period
of 20 ps. Waveforms of VOUT for Nb- and Al-contact JJ-FET inverters with(c) and (d) CL = 1 fF, and (e) and (f) CL = 5 fF, respectively. For reference,
the gate capacitance is 0.7 fF for W = 1 µm and L = 20 nm. IBias is
slightly reduced to 12 µA from that in the static model for the Nb-contact
JJ-FET inverter. IBias and VT are 1.06 µA and −0.2 mV for the Al-contact
JJ-FET inverter.
TABLE I
Q OF JJ-FET INVERTER
Q ≈ 4 is the critical value for the Nb-contact JJ-FET inverter
to be properly reset and slightly lower for the Al-contact
device as Q ≈ 2.5. The critical value of Q is closely related
to the ratio of IBias/IC(VG,Hi) due to the hysteretic I–V
characteristics. This ratio is 0.5 and 0.7 for the parameter set
our Nb- and Al-contact JJ-FET inverter assumes, in agreement
with the ratio of return current over IC corresponding to the
critical Q in a hysteretic JJ [16].
Similarly, we can write Q for a JJ-FET NOR gate as
QNOR = R
2C(IC1 + IC2)
0/2pi
= pi
3/2V0(2CJ + CL)√
2eCG · (√VIN1 − VT + √VIN2 − VT) (11)
where IC1 and IC2 are the critical current of the two JJ-FETs.
Fig. 8 presents the results of transient analysis for JJ-FET NOR
gates with the same device parameters used in JJ-FET inverters
and doubled IBias. Fig. 8(a)–(d) shows the input waveforms
for the Nb- and Al-contact JJ-FET NOR gates, respectively.
The signal at VIN2 has twice the period and is in phase with
Fig. 8. Square waveforms of VIN1 for (a) Nb-contact JJ-FET NOR gate(0 ∼ 6 mV) and (b) Al-contact JJ-FET NOR gate (0 ∼ 1.1 mV) with a
period of 20 ps. Square waveforms of VIN2 for (c) Nb- and (d) Al-contact
JJ-FET NOR gate with a period of 40 ps. Waveforms of VOUT for the
Nb- and Al-contact JJ-FET NOR gate with (e) and (f) CL = 1 fF,(g) and (h) CL = 2.5 fF, (i) CL = 5 fF, and (j) CL = 7 fF, respectively.
IBias = 24 and 2 µA for Nb- and Al-contact JJ-FET NOR gates.
that at VIN1 to enumerate all four possible logic combinations
at the inputs. The output waveforms for the Nb- and Al-
contact JJ-FET NOR gates are shown in Fig. 8(e) and (f) with
CL = 1 fF and Fig. 8(g) and (h) with CL = 2.5 fF. Finally,
output waveforms for the Nb- and Al-contact JJ-FET NOR
gates with CL = 5 and 7 fF are shown in Fig. 8(i) and (j).
Table II summarizes the values of Q associated with different
combinations of VIN1, VIN2, and CL for both Nb- and Al-
contact JJ-FET NOR gates. Again, the values of CL and, there-
fore, Q are crucial to determine the behavior of the JJ-FET
NOR gates. In Fig. 8(e) and (f), VOUT correctly reproduces
the response of a NOR gate, e.g., VOUT only becomes finite
when both inputs are low. However, when CL is increased from
1 to 2.5 fF, VOUT fails to be reset to zero when only one of
the inputs switches from low to high and outputs an undefined
intermediate state [see Fig. 8(g) and (h)]. When CL is further
increased to 5 and 7 fF for the Nb- and Al-contact JJ-FET
NOR gates, VOUT remains finite even when both inputs switch
to high. Consequently, there are two undefined intermediate
states, as shown in Fig. 8(i) and (j).
C. Global Clock to Reset JJ-FETs
In the previous section, we showed that the Q = 0 approxi-
mation is not applicable if the fan-out load capacitance is taken
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5372 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019
TABLE II
Q OF JJ-FET NOR GATE
into account. The JJ-FETs usually enter the underdamped
regime and become hysteretic, at least when inputs are low.
On the other hand, JJ-FETs can turn back to overdamped
when inputs switch from low to high, thanks to a low Q
from optimized design. In this case, we can harness the
unique feature of the superconducting logic device, where tf is
determined by τRL . Thus, a promising design of JJ-FET logic
gate resembles the dynamic logic gate, featuring a precharge
of VOUT and monotonically rising VIN during evaluation.
Voltage-state JJ logic device is not a new concept. Decades
ago, the transformation of a JJ into switching element was
realized through magnetic coupling or current injection into
the channel [4]. Those JJs were underdamped with high Q
due to the obsolete fabrication technology and capacitor device
geometry and required an ac power supply and other circuit
elements to isolate the output from the input. An ac power
supply was used since, in an underdamped JJ, resetting from
the resistive to superconducting state requires the ratio of
IJ/I C to be lowered to a small value for a period of time
and this can only be achieved by lowering IBias. On the other
hand, the JJ-FET is nonreciprocal and has a low Q thanks to
modern transistor fabrication technology and coplanar geom-
etry. Moreover, the JJ-FET has a gate-tunable IC and can
conceivably be reset to the superconducting state by increasing
VG − VT. We find that a short voltage pulse can be applied
to VIN to temporarily boost VG − VT and reset VOUT back
to zero. Fig. 9(a) and (b) presents the output waveforms for
the Nb- and Al-contact JJ-FET inverters with CL = 5 fF
in response to a square waveform with a period of 50 ps.
Due to the underdamped operation, VOUT remains finite when
VIN switches to high. Fig. 9(c) and (d) shows the results
of VOUT with an addition of clock signals (VCLK) with the
same period in red and blue lines, respectively. VCLK includes
a 5-ps voltage pulse of 10 and 4 mV for the Nb- and Al-
contact JJ-FET inverters, which is applied at the rising edge
of VIN. The pulsewidth (tPW) can be narrower with a larger
amplitude for higher speed, e.g., a pulse of 20 mV, and 2 ps
can reset this Nb-contact JJ-FET inverter. Conversely, tPW of
such a transient pulse can be relaxed with a lower operating
frequency. A simplification is made that VIN and VCLK add to
each other. VOUT is successfully restored to zero with VCLK
added. Similarly, Fig. 9(e) and (f) shows the results of the
voltage pulse activated at the falling edge of VIN, where red
and blue lines represent VOUT and VCLK. Though the rise of
VOUT is delayed, it does reach the target value. Therefore,
a global clock mechanism can be introduced if underdamped
operation cannot be avoided at the expense of lower speed.
Fig. 9. (a) and (b) Output waveforms of Nb- and Al-contact JJ-FET
inverters, respectively, without VCLK. (c) and (d) Output waveforms with
VCLK switching from low to high at the VIN rising edge. (e) and (f) Output
waveforms with VCLK switching from low to high at the VIN falling edge.
VCLK is indicated in blue curves in (c)–(f). The other parameters are the
same as those used in Fig. 7.
Indeed, since the logic value of VOUT must be evaluated
when VCLK = 0, the waveform half-period should exceed
tPW + tr + tH, where tH is the hold time. It is noteworthy
that VCLK may be synchronized with the clock in a dynamic
logic gate.
IV. DISCUSSION
The model we employ in this article ignores the mesoscopic
effects and applies to ideal contacts. It is, therefore, necessary
to examine the validity of our assumptions. First, mesoscopic
effects can potentially change the IJ value. For example, while
Kondo resonances can suppress this magnitude, we expect a
minimal effect for the device in the short ballistic regime [21].
The experimentally observed V0 value is close to the ballistic
limit pi [11], suggesting that the JJ-FET is not operating
in the Kondo effect-dominated regime. Second, mesoscopic
effects can change the dependence of IJ on ϕ(t). Fortunately,
this current-phase relation remains sinusoidal for a short
ballistic junction in nanoscale [22]. On the other hand, in
a realistic device, carriers will observe a tunnel barrier at
the channel/contact interface, a key ingredient to validate the
sinusoidal current-phase relation [23]. It is noteworthy that
the current magnitude is similar to the case where there is no
tunnel barrier, since the reduction of current due to normal
reflections at the disordered junction is compensated by the
current increase from Andreev reflections [24]. We, therefore,
assess that a realistic JJ-FET with finite transparency between
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WEN et al.: JJ-FETs FOR BOOLEAN LOGIC CRYOGENIC APPLICATIONS 5373
the channel and contacts can still achieve V0 at the short
ballistic limit.
Additionally, in our analysis throughout, we have assumed
the JJ-FET gate overdrive VG − VT controls the gate charge
(qG) and therefore IC by modulating the weak link in the
channel. However, this unidirectional JJ-FET model where IDS
is set by qG without a back reaction is thermodynamically
unsound [25]. The energy of a JJ-FET is
E J F = q
2
G
2W LCG
+
2e
IC(qG)(1− cos ϕ(t)) (12)
where IC(qG) is IC with gate charge qG. Since VG − VT =
∂ EJF/∂qG, we find qG is reduced, compared to the unidirec-
tional model
qG = W LCG(V G − VT)−β(qG)2e (1− cos ϕ(t)) (13)
where β(qG) is β with gate charge qG. The back reaction
is negligible when the RHS second term is small, namely
γ = β(qG)/2eW LCG(VG−VT) 1, a condition which does
not hold for the logic device operation regime discussed here.
For the parameters used in the Nb-contact JJ-FET inverter at
zero VIN, i.e., VG−VT = 1.2 mV, W = 1 µm, and L = 50 nm,
the two terms of (13) RHS are comparable.
We note that β decreases with increasing VG−VT; hence, the
back reaction becomes particularly important when VIN is low.
This implies that if we ignore the back reaction, the channel
can be fully depleted and VOUT will be in an undefined
state. The back reaction can be compensated by shifting VT
to a more negative value. For example, the operation of an
Nb-contact JJ-FET inverter is restored by setting VT = −3.5
mV. While the back reaction adds extra complexity to the
design of JJ-FET logic gates, if it is properly compensated
at zero VIN, at high VIN, its impact is reduced.
It is of interest to investigate how advances in nanofabrica-
tion will influence the JJ-FET logic gates. Transistor scaling
effectively produces smaller L and larger CG. In order to val-
idate the model used in this article, L needs to be sufficiently
short compared to the superconducting coherence length
ξ0 = vF
pie
=
2√2piCG(VG − VT)
m∗pie3/2
(14)
where vF and m∗ are the Fermi velocity and effective electron
mass in the semiconductor channel, which are crucial to
achieve a significant ξ0 at the low VG −VT required by JJ-FET
logic gates. A large CG in the scaled JJ-FET device promises
a long ξ0 and small γ . Alternatively, it may also allow a
lower VG − VT to reduce power consumption. However, Q
will increase consequently, which imposes a design tradeoff
of CG and potentially justifies the necessity of VCLK.
The choice of superconductor contacts is another important
factor. Choosing a low contact has various benefits. In light
of the requirements of finite VG − VT for reasonable γ, ξ0,
and Q, and appreciable αR for signal restoration, we usually
have VG − VT ∼ . Then, we can approximate the power
consumption P ∝ ICV0 ∝ 5/2 and power-delay product
PτRL ∝ 3/2, indicating that smaller yields more efficient
JJ-FET logic gates. Additionally, we have Q ∝ √ and
ξ0 ∝ 1/
√
, promoting the overdamped operation and
relaxing the requirement of reduced L and m∗. However,
we also have γ ∝ 1/√, which indicates a low JJ-FET is
less immune to the back reaction. Also, a larger is favored
for faster speed given τRL ∝ 1/. The above arguments
impose a design tradeoff for .
Although JJ-FET logic gates cannot relax the requirement
of ultraprecise control of VT compared with cryogenic CMOS,
they provide a better circuit tolerance in the sense that JJ-FETs
are always in the ON state while a CMOS device has to make
a transition between ON and OFF states within the operating
voltage window. Moreover, the speed of the JJ-FET logic
gate is limited by τRL if designed properly for overdamped
operation, as opposed to the RC time constant in a CMOS
device, which can be unacceptably high for the low carrier
concentrations due to small VDD at cryogenic temperature.
On the other hand, JJ-FET logic gates possess a smaller
break-even operating voltage than cryogenic CMOS if we
factor in the static power consumption. JJ-FET logic gates
also demonstrate great compatibility with emerging material
platforms, e.g., the III–V quantum-well JJ-FET is a depletion-
mode n-type device [11]; the graphene channel can reach its
charge neutrality point at a slightly negative VG [10] and the
proposed JJ-FET logic gates can circumvent the issue of low
ON–OFF ratio for CMOS [26], [27]. Moreover, the low m∗ and
high vF in III–V quantum-well, and especially in graphene,
mitigate the conflict between long ξ0 and low VG − VT, e.g.,
Dirac electrons in graphene have an ξ0 = 70 and 470 nm in
Nb- and Al-contact JJ-FETs [28], respectively.
V. CONCLUSION
When cooling costs are factored in, the operating voltage of
CMOS-based circuits has to be scaled down significantly for
cryogenic computing to provide a net power reduction. JJ-FET
Boolean logic can harness the superconducting property of
these devices at these cryogenic temperatures and provide low
operating voltage on the order of superconductor gap voltage.
Assuming a short ballistic transport length, we employ the
static and RCSJ model to capture the behavior of JJ-FET
logic gates with fan-out. A global clock can mitigate the
underdamped operation, if necessary. Transistor scaling and
the choice of different superconducting contacts have notable
impacts on the device operation. For example, reduced
gate dielectric thickness guarantees better back-reaction
immunity but favors underdamped operation, and larger gap
voltage ensures a faster operation speed but at the cost of
reduced coherence length, hence channel length. We find
JJ-FET logic gates can be a promising candidate for dynamic
logic elements with ultrashort fall times and can utilize the
advantages of emerging channel materials like III–V quantum
wells and graphene.
ACKNOWLEDGMENT
The authors would like to thank S. K. Banerjee and
R. Pillarisetty for discussions.
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学霸联盟
Josephson Junction Field-Effect Transistors for
Boolean Logic Cryogenic Applications
Feng Wen , Javad Shabani, and Emanuel Tutuc , Senior Member, IEEE
Abstract— Josephson junction FETs (JJ-FETs) share
design similarities with MOSFETs, except for the
source/drain contacts being replaced by superconductors.
Similarly, the super current due to proximity effect is
tunable by the gate voltage. In light of recent advances in
novel materials and fabrication techniques, we examine
here the feasibility of JJ-FET-based Boolean logic and
memory elements for cryogenic computing. Using a 2-D
ballistic transport JJ-FET model, we implement circuit-level
simulations for JJ-FET logic gates and discuss criteria for
realizing signal restoration, as well as fan-out. We show
that the JJ-FET is a promising candidate for very low-
power, clocked voltage-level dynamic logic at cryogenic
temperatures.
Index Terms— Ballistic transport, Josephson junction
(JJ), superconducting logic device.
I. INTRODUCTION
REDUCING temperature (T ) improves several key devicemetrics of the MOSFETs. Examples include enhanced
channel mobility and reduced subthreshold swing (SS), which
scales linearly with T as SS = 2.3 (kT/e)/decade; k is
Boltzmann’s constant and e is the electron charge. Channel
injection efficiency can be improved in the absence of phonon
scattering [1], and the resistance of metal interconnects is
expected to decrease at lower temperatures. It is, therefore,
important to investigate under what conditions cryogenic com-
puting provides a net benefit in terms of dissipated energy
per switching operation and whether other devices can offer
a benefit in performance at reduced temperatures. For a given
technology with supply voltage VDD, the energy dissipated
per switching operation is CVDD2/2, where C represents the
device capacitance. Assuming VDD(T ) can be reduced at lower
T , by requiring that the total energy dissipated per switching
operation, including the cooling cost, does not exceed the room
Manuscript received September 13, 2019; accepted October 22, 2019.
Date of current version November 27, 2019. This work was supported
in part by the National Science Foundation under Grant DMR-1507654
and in part by Intel Corporation. The review of this article was arranged
by Editor S. Hong. (Corresponding author: Emanuel Tutuc.)
F. Wen and E. Tutuc are with the Microelectronics Research Center,
Department of Electrical and Computer Engineering, The University of
Texas at Austin, Austin, TX 78758 USA (e-mail: wenfeng@utexas.edu;
etutuc@mer.utexas.edu).
J. Shabani is with the Center for Quantum Phenomena, Department of
Physics, New York University, New York, NY 10003 USA.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2019.2951634
temperature value, we arrive at the following energy balance
equation:
CVDD(300 K)2
2
= CVDD(T )
2
2
+ 300 K−T
T
· CVDD(T )
2
2
. (1)
The second term on the right-hand side (RHS) of (1) represents
the cooling cost at the ideal Carnot efficiency, corresponding
to reservoir temperatures of 300 K and T . Equation (1) leads
to the following simple scaling law for the operating voltage to
break even in the ideal cooling limit:
VDD(T ) = VDD(300 K)
√
T
300 K
. (2)
For example, a VDD value of 0.7 V at room temperature will
translate to a break-even value of 83 mV at 4.2 K, the liquid
He boiling point, which is further reduced to ∼26 mV if
one factors in realistic cooling efficiencies of 5%–10% [2].
The gate delay associated with load and parasitic capacitance
being charged/discharged will scale with reducing VDD, while
the transit time delay of channel being switched may not
scale down proportionally because of low Fermi velocity at
low carrier concentration and reduced thermal excitation of
carriers [3]. While the above arguments contain a number of
simplifications, they clearly indicate that cryogenic computing
using CMOS concepts is subject to significant constraints if a
net benefit is expected over room-temperature operation with
cooling cost factored in. It is, therefore, highly relevant to
examine if other devices operating at or below the break-even
VDD value may be used for cryogenic computing applications.
Josephson-logic devices can operate at VDD values in the
millivolt range utilizing superconductivity [4], the most spec-
tacular material property that emerges at low temperatures as
a result of electrons forming Cooper pairs. The devices are
based on the Josephson junction (JJ), a two-terminal device
consisting of two superconductor contacts separated by a
weak link, allowing current flow without dissipation (super-
current) due to proximity effect. The feasibility of JJ-FET,
a three-terminal device with gate-tunable supercurrent, for
logic operation was discussed decades ago [5], [6]. The JJ-FET
design is similar to a MOSFET except that the source and
drain are superconducting at cryogenic temperatures, and the
channel length is sufficiently short to allow coherent transport
of Cooper pairs through the channel. JJ-FETs have been
experimentally demonstrated on various material platforms,
including Si, Ge, and III–V compounds [7]–[9]. Advances in
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5368 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019
Fig. 1. Schematic of a JJ-FET consisting of superconducting source
and drain, metal gate, oxide, semiconductor channel, and insulating
substrate. The length scales L, ξ0, and λ are indicated. The scatter-
ing or destruction of Cooper pairs will occur if L is greater than λ or ξ0,
respectively, as shown in the figure. Arrows: Cooper pairs or electrons
motion.
fabrication techniques and emerging channel materials, such
as nanowires, III–V quantum-wells, and graphene, as well as
the development of transparent semiconductor/superconductor
interfaces render the topic of JJ-FETs timely [10]–[13].
In this article, we address the feasibility of JJ-FETs for digi-
tal applications. We employ a JJ-FET device model that allows
gate-controlled ballistic and coherent transport of Cooper
pairs through the channel to examine the criteria for signal
restoration of several logic gates. We present the results of
transient analysis of JJ-FET logic gates, evaluate the impact
of fan-out on device behavior, and discuss various design
considerations.
II. JJ-FET DEVICE MODEL
We begin by introducing a device model for the JJ-FET.
The device, schematically shown in Fig. 1, has the following
key length scales: the channel length (L), the Cooper pair
coherence length (ξ0), and Cooper pair mean free path (λ).
Depending on the interplay between L, ξ0, and λ, the JJ can
operate in either short or long ballistic or diffusive regimes.
The JJ is short if L < ξ0 or long if L > ξ0. The Cooper pair
transport is ballistic if L < λ or diffusive if L > λ.
Here, we consider the case of a short ballistic JJ device,
which satisfies the Ambegaokar–Baratoff formula [14]
V0 = IC · RN = pi (3)
where IC is the critical current, RN is the normal resistance
of the JJ, and is half the superconductor gap voltage. The
conductance of a 2-D ballistic transport layer, divided by the
average velocity along the channel direction, is
gn = W ·2e
2
h
· 2
pi
· √2pin (4)
where W is the device width, h is the Planck constant, and
n is the carrier density. The carrier density can be related to
Fig. 2. Calculated I–V characteristics for JJ-FETs with W = 1 µm,
effective SiO2 oxide thickness of 1 nm (CG = 3.45 µF/cm2) using(a) Nb and (b) Al contacts. The VG −VT values indicated in the figure are
changed in (a) 1- and (b) 0.5-mV increments.
gate capacitance (CG) and gate voltage (VG) via n = CG(VG−
VT)/e; VT is the threshold voltage. Using (3) and (4)
IC = gn·V0 = 2V 0W ·2eh ·
√
2eCG(VG − VT)
pi
. (5)
It is instructive to introduce an equivalent conductance for the
IC dependence on VG as
β = d IC
dVG
= V0 dgndVG = V0W ·
2e
h
·
√
2eCG
pi(VG − VT) . (6)
If we assume the device is in the overdamped limit, where
I–V characteristics are nonhysteretic [15], [16], the static I–V
characteristics are relatively simple
VDS = RN
√
I 2DS − I 2C (IDS > IC)
VDS = 0 (IDS < IC) (7)
where VDS is the voltage drop across the drain and source con-
tacts and IDS is the drain current. Because Nb and Al are two
commonly used superconductors [17], [18], we consider here
the cases where the source/drains consist of either Nb or Al
with values of 1.5 or 0.22 mV, respectively [19]. Fig. 2
shows the static I–V characteristics of JJ-FETs with the two
metal contacts.
A critical question for a logic gate is if the output voltage
is sufficiently large to switch the next stage. To address this
question let us assume the output of one JJ-FET is directly
driving the gate of a second JJ-FET, whose IC value, in turn,
needs to be sufficiently modulated for a switch. Equation (7)
indicates that VDS will be of the order of V0 if IDS is
comparable to IC [4]. The relative change in IC corresponding
to a gate swing of V0 is [20]
αR = βV0IC =
V0
2(VG − VT) . (8)
To achieve signal restoration αR ∼ 1, hence VG − VT needs
to be comparable to V0. This is an intrinsic requirement of
JJ-FET logic gate, independent of device scaling and geometry.
Fig. 3 shows the plots of αR against VG − VT for both
Nb- and Al-contact JJ-FETs.
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WEN et al.: JJ-FETs FOR BOOLEAN LOGIC CRYOGENIC APPLICATIONS 5369
Fig. 3. Calculated αR versus VG − VT for (a) Nb- and (b) Al-contact
JJ-FET.
Fig. 4. Schematics of JJ-FET (a) inverter, (b) NOR gate, and (c) SRAM.
III. JJ-FET LOGIC GATES
A. Static Analysis
In this section, we consider logic gates based on JJ-FETs.
Fig. 4(a)–(c) shows the schematics of the JJ-FET inverter, NOR
gate, and static random access memory (SRAM), respectively.
A NOR gate is universal and can be the building block for any
combinatorial logic circuit. In this article, we assume all logic
devices are biased with ideal dc current (IBias) sources for
simplicity. The logic gates operate as follows. For a JJ-FET
inverter [see Fig. 4(a)], when the input voltage at the gate
(VIN) is at logic low (VG,Lo), the corresponding IC < IBias
and the JJ-FET is resistive, leading to a finite output voltage
(VOUT). On the other hand, when VIN is at logic high (VG,Hi),
the corresponding IC > IBias, the JJ-FET is superconducting,
and VOUT is zero. Consequently, we have VG,Lo = 0 since
the JJ-FETs are cascaded in logic circuits. Signal restoration
indicates the finite VOUT at VIN = VG,Lo at least equal to
VG,Hi to drive the input of the next stage, i.e., the same input–
output swing. Similarly, in a JJ-FET NOR gate [see Fig. 4(b)],
the sum of IC of the two JJ-FETs is smaller than IBias only
when both inputs are at logic low, leading to a finite VOUT
and zero otherwise. Connecting two JJ-FET inverters back to
back yields an SRAM cell [see Fig. 4(c)], where V1 and V2
will reach a stable state of complementary values.
Next, we design the JJ-FET inverter using the static model
and investigate its performance, ignoring any parasitic capac-
itance and resistance of the JJ-FET itself. Though this model
may be oversimplified, it sheds lights on the dc operating
point, i.e., VT and IBias values will produce the same input–
output swing, namely VG,Hi = VOUT(VG,Lo) = RN(VG,Lo) ·√
(I 2Bias− I 2C(VG,Lo)) and optimal power or speed; the variables
in parentheses denote the VIN values. We can estimate the
Fig. 5. (a) τmin = min(tr + tf) among bias points with their respective
equal input–output swing at each |VT|. (b) Transient analysis result with
minimum τmin using the following set of parameters: Swing of input–
output = 5.9 mV, W = 1 µm, VT = −1.2 mV, and IBias = 15.1 µA. The
superconducting contacts are Nb.
power consumption of the JJ-FET as ∝ IBiasVG,Hi. Hypotheti-
cally, we could have an arbitrarily small swing and thus power
consumption by choosing IBias close to IC(VG,Lo). We could
also have an arbitrarily large swing since RN(VG,Lo) diverges
when VT approaches zero. Hence, for any given swing,
we have a solution to the bias point by appropriately choosing
VT and IBias, albeit with tradeoffs. Therefore, we chose to
design the bias point of the logic gates based on speed.
The rising delay (tr) is not expected to be reduced compared
to that of the traditional counterpart, e.g., an NMOS inverter,
because when VIN switches to low, the JJ-FET becomes
resistive instead of being cut off. Moreover, the JJ-FET draws
additional current to the resistive component, namely the
Josephson current (IJ), effectively further slowing down the
charging speed at the output node. On the other hand, IJ will
assist to discharge the output node when VIN switches to high.
The falling delay (tf) is, therefore, smaller than that of an
NMOS inverter, and more importantly, the superconducting
JJ-FET can fully discharge the output. Fig. 5(a) presents the
plot of minimum total delay τmin as a function of |VT| for an
Nb-contact JJ-FET inverter. The device has the same geometry
as that assumed in Fig. 2 and an output capacitance CL =
10 fF, chosen as fan-out of four plus interconnect capacitance.
For reference, the gate capacitance of a JJ-FET with W =
1 µm and L = 50 nm is 1.7 fF. We note the actual value of CL
is insignificant to demonstrate the logic operation here, since
the characteristics of JJ-FET logic gates using the static I–V
model will not change with CL, except for the delay to scale
linearly. For a fixed VT, a given IBias > IC(VG,Lo) decides
VOUT(VG,Lo) and therefore the output swing. Meanwhile, IBias
cannot exceed IC(VOUT(VG,Lo)) so there is a matched input
swing. Hence, we have multiple solutions of various IBias to
the bias point at each VT. We first determine those quiescent
points, then extract tr and tf for individual point from transient
analysis, and finally obtain τmin at that VT as the minimum of
(tr + t f) among those points. Effectively, the curve in Fig. 5(a)
is the projection of a trace along the contour plot for (tr + t f)
against VT and IBias. We find that τmin reaches a global
minimum at VT ≈ −0.8, where the VIN swing is ≈ 4.
Using this bias point, an example of transient analysis for the
Nb-contact JJ-FET inverter is shown in Fig. 5(b). It is clear
that the falling edge of VOUT is more linear than exponential
compared with the rising edge thanks to IJ, which remains
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5370 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019
Fig. 6. (a) Transient response of the node voltages at the outputs of the
two JJ-FETs in an SRAM cell. (b) Voltage transfer curves indicating the
two stable operation points. The static noise margin is indicated with a
dashed-line box. CL = 1 fF at both outputs. The superconductor contacts
are Nb.
∼ IC and does not linearly decrease with VOUT as the resistive
counterpart. The tr and tf values are 6.4 and 2 ps in this case.
Similarly, a NOR gate can be constructed by simply doubling
IBias since 2IBias < IC(VG,Hi) + IC(VG,Lo).
Applying the same set of parameters for the Nb-contact
JJ-FET inverter in Fig. 5(b), Fig. 6(a) shows the transient
response of the output voltages V1 and V2 for the two JJ-FET
inverters in an SRAM cell. The initial voltage values at the
two outputs are associated with the metastable state (V1 =
V2 ≈ 1.5 mV). In the presence of any disturbance, which is
ubiquitous in an actual circuit, the feedback loop will stabilize
the two inverters to their respective conditions. The final state
is one of the two stable states, where V1 and V2 have opposite
logic values. In this example, the metastable state ends due
to a disturbance at 25 ps and the cell reaches the stable state
where V1 = 5.9 mV and V2 = 0 mV, representing a bit “1”
stored in the cell. Other initial conditions will work as if the
disturbance is already given. Fig. 6(b) presents the voltage
transfer curves of the two JJ-FETs in the same SRAM cell
with the static noise margin indicated in a dashed-line box.
The intersection of the two curves in the middle indicates the
metastable state while the two at the ends represent the stable
states pointed by arrows.
B. Dynamic Analysis
Although we can design the dc operating point of JJ-FET
logic gates with the static model, we have made a critical
assumption that the JJ-FETs are overdamped in the transient
analysis. If a JJ works in the overdamped regime and carries
a current exceeding IC, it is nonhysteretic and will become
superconducting immediately when the current falls below IC.
For an overdamped and resistive JJ-FET, it means the transistor
will become superconducting as soon as VG is increased such
that IC > IDS. However, a JJ or JJ-FET is overdamped only
when the Stewart–McCumber parameter Q = 2pi R2C IC/ 0
is small (Q 4) [15], [16], where R and C are the
resistance and capacitance across the junction, and 0 is the
magnetic flux quantum. On the other hand, a JJ becomes
underdamped if Q is large, which means it remains in the
resistive state even when the junction current is reduced below
IC, leading to I–V hysteresis. The assumption of overdamped
operation becomes questionable if we acknowledge that a
logic device has fan-out, and therefore, has larger C as well
as Q than a single transistor. Moreover, by ignoring the
Josephson inductance LC = /2eIC, the estimation of gate
delay is no longer accurate, as the dominant time constant
of an overdamped JJ-FET is the Josephson time constant
τRL = LC/RN = /(ne). To address these dilemmas, we
implement the resistively and capacitively shunted junction
(RCSJ) model to describe the device. The I–V characteristics
are controlled by the time-dependent variable ϕ(t), which
is the macroscopic phase difference of the superconducting
contacts
IDS(t) = C dVDS(t)dt +
VDS(t)
R
+ ICsinϕ(t)
VDS(t) = 2e ·
dϕ(t)
dt
(9)
where ICsinϕ(t) represents IJ. We assume the load is purely
capacitive and ignore the resistance of the biasing circuitry.
Therefore, a JJ-FET inverter’s device resistance R = RN and
capacitance C = CL+CJ, where CJ is the junction capacitance
assuming gate capacitance splits symmetrically to the source
and drain. The gate-tunable Q for a JJ-FET inverter writes
Qinv = R
2C IC
0/2pi
= pi
3/2V0(CJ + CL)√
2eCG(VIN − VT) (10)
where CJ and CL are normalized to W = 1 µm of the active
JJ-FET. We have CL ∝ CG if the output is driving inputs of
other JJ-FETs, and hence, for a JJ-FET logic inverter, Qinv ∝
(CG/(VG − VT))1/2.
Fig. 7 presents the results of transient analysis for both
Nb- and Al-contact JJ-FET inverters with device parameters
adapted from the static analysis based on VT ≈ −0.8.
Fig. 7(a) and (b) shows the input waveforms for the Nb- and
Al-contact JJ-FET inverters, respectively. Fig. 7(c) and (d)
shows the output waveforms for the Nb- and Al-contact
JJ-FET inverters with CL = 1 fF. Similarly, the output
waveforms for the Nb- and Al-contact JJ-FET inverters with
CL = 5 fF are shown in Fig. 7(e) and (f). The values of
CL in the dynamic analysis section are chosen to represent
the respective operation regime whether hysteresis will latch
the JJ-FET in the resistive state or not. Table I summarizes the
values of Q associated with different CL and zero VIN for both
Nb- and Al-contact JJ-FET inverters. Comparing the output
waveforms to those using the static model, superimposed
oscillations emerge because of the Josephson effect. Similar
to a parallel RLC circuit, the amplitude is attenuated by larger
CL, and the frequency is higher for the Nb-contact device due
to smaller LC. The Nb-contact JJ-FET inverter is significantly
faster than its Al-contact counterpart, e.g., tf = 0.25 and
2.5 ps, respectively, with CL = 1 fF. The difference in
their tf is comparable to that of their τRL . If we compare
Fig. 7(c) and (d) with Fig. 7(e) and (f), a distinct difference
that can be seen is that JJ-FET inverters fail to be reset into the
superconducting states when VIN switches from zero to high
when CL is increased from 1 to 5 fF. Consequently, the finite
Q must be accounted for when designing JJ-FET logic gates
to avoid an undefined VOUT. In the simulation, we find
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WEN et al.: JJ-FETs FOR BOOLEAN LOGIC CRYOGENIC APPLICATIONS 5371
Fig. 7. Square waveforms of VIN for (a) Nb-contact JJ-FET inverter(0 ∼ 6 mV) and (b) Al-contact JJ-FET inverter (0 ∼ 1.1 mV) with a period
of 20 ps. Waveforms of VOUT for Nb- and Al-contact JJ-FET inverters with(c) and (d) CL = 1 fF, and (e) and (f) CL = 5 fF, respectively. For reference,
the gate capacitance is 0.7 fF for W = 1 µm and L = 20 nm. IBias is
slightly reduced to 12 µA from that in the static model for the Nb-contact
JJ-FET inverter. IBias and VT are 1.06 µA and −0.2 mV for the Al-contact
JJ-FET inverter.
TABLE I
Q OF JJ-FET INVERTER
Q ≈ 4 is the critical value for the Nb-contact JJ-FET inverter
to be properly reset and slightly lower for the Al-contact
device as Q ≈ 2.5. The critical value of Q is closely related
to the ratio of IBias/IC(VG,Hi) due to the hysteretic I–V
characteristics. This ratio is 0.5 and 0.7 for the parameter set
our Nb- and Al-contact JJ-FET inverter assumes, in agreement
with the ratio of return current over IC corresponding to the
critical Q in a hysteretic JJ [16].
Similarly, we can write Q for a JJ-FET NOR gate as
QNOR = R
2C(IC1 + IC2)
0/2pi
= pi
3/2V0(2CJ + CL)√
2eCG · (√VIN1 − VT + √VIN2 − VT) (11)
where IC1 and IC2 are the critical current of the two JJ-FETs.
Fig. 8 presents the results of transient analysis for JJ-FET NOR
gates with the same device parameters used in JJ-FET inverters
and doubled IBias. Fig. 8(a)–(d) shows the input waveforms
for the Nb- and Al-contact JJ-FET NOR gates, respectively.
The signal at VIN2 has twice the period and is in phase with
Fig. 8. Square waveforms of VIN1 for (a) Nb-contact JJ-FET NOR gate(0 ∼ 6 mV) and (b) Al-contact JJ-FET NOR gate (0 ∼ 1.1 mV) with a
period of 20 ps. Square waveforms of VIN2 for (c) Nb- and (d) Al-contact
JJ-FET NOR gate with a period of 40 ps. Waveforms of VOUT for the
Nb- and Al-contact JJ-FET NOR gate with (e) and (f) CL = 1 fF,(g) and (h) CL = 2.5 fF, (i) CL = 5 fF, and (j) CL = 7 fF, respectively.
IBias = 24 and 2 µA for Nb- and Al-contact JJ-FET NOR gates.
that at VIN1 to enumerate all four possible logic combinations
at the inputs. The output waveforms for the Nb- and Al-
contact JJ-FET NOR gates are shown in Fig. 8(e) and (f) with
CL = 1 fF and Fig. 8(g) and (h) with CL = 2.5 fF. Finally,
output waveforms for the Nb- and Al-contact JJ-FET NOR
gates with CL = 5 and 7 fF are shown in Fig. 8(i) and (j).
Table II summarizes the values of Q associated with different
combinations of VIN1, VIN2, and CL for both Nb- and Al-
contact JJ-FET NOR gates. Again, the values of CL and, there-
fore, Q are crucial to determine the behavior of the JJ-FET
NOR gates. In Fig. 8(e) and (f), VOUT correctly reproduces
the response of a NOR gate, e.g., VOUT only becomes finite
when both inputs are low. However, when CL is increased from
1 to 2.5 fF, VOUT fails to be reset to zero when only one of
the inputs switches from low to high and outputs an undefined
intermediate state [see Fig. 8(g) and (h)]. When CL is further
increased to 5 and 7 fF for the Nb- and Al-contact JJ-FET
NOR gates, VOUT remains finite even when both inputs switch
to high. Consequently, there are two undefined intermediate
states, as shown in Fig. 8(i) and (j).
C. Global Clock to Reset JJ-FETs
In the previous section, we showed that the Q = 0 approxi-
mation is not applicable if the fan-out load capacitance is taken
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5372 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019
TABLE II
Q OF JJ-FET NOR GATE
into account. The JJ-FETs usually enter the underdamped
regime and become hysteretic, at least when inputs are low.
On the other hand, JJ-FETs can turn back to overdamped
when inputs switch from low to high, thanks to a low Q
from optimized design. In this case, we can harness the
unique feature of the superconducting logic device, where tf is
determined by τRL . Thus, a promising design of JJ-FET logic
gate resembles the dynamic logic gate, featuring a precharge
of VOUT and monotonically rising VIN during evaluation.
Voltage-state JJ logic device is not a new concept. Decades
ago, the transformation of a JJ into switching element was
realized through magnetic coupling or current injection into
the channel [4]. Those JJs were underdamped with high Q
due to the obsolete fabrication technology and capacitor device
geometry and required an ac power supply and other circuit
elements to isolate the output from the input. An ac power
supply was used since, in an underdamped JJ, resetting from
the resistive to superconducting state requires the ratio of
IJ/I C to be lowered to a small value for a period of time
and this can only be achieved by lowering IBias. On the other
hand, the JJ-FET is nonreciprocal and has a low Q thanks to
modern transistor fabrication technology and coplanar geom-
etry. Moreover, the JJ-FET has a gate-tunable IC and can
conceivably be reset to the superconducting state by increasing
VG − VT. We find that a short voltage pulse can be applied
to VIN to temporarily boost VG − VT and reset VOUT back
to zero. Fig. 9(a) and (b) presents the output waveforms for
the Nb- and Al-contact JJ-FET inverters with CL = 5 fF
in response to a square waveform with a period of 50 ps.
Due to the underdamped operation, VOUT remains finite when
VIN switches to high. Fig. 9(c) and (d) shows the results
of VOUT with an addition of clock signals (VCLK) with the
same period in red and blue lines, respectively. VCLK includes
a 5-ps voltage pulse of 10 and 4 mV for the Nb- and Al-
contact JJ-FET inverters, which is applied at the rising edge
of VIN. The pulsewidth (tPW) can be narrower with a larger
amplitude for higher speed, e.g., a pulse of 20 mV, and 2 ps
can reset this Nb-contact JJ-FET inverter. Conversely, tPW of
such a transient pulse can be relaxed with a lower operating
frequency. A simplification is made that VIN and VCLK add to
each other. VOUT is successfully restored to zero with VCLK
added. Similarly, Fig. 9(e) and (f) shows the results of the
voltage pulse activated at the falling edge of VIN, where red
and blue lines represent VOUT and VCLK. Though the rise of
VOUT is delayed, it does reach the target value. Therefore,
a global clock mechanism can be introduced if underdamped
operation cannot be avoided at the expense of lower speed.
Fig. 9. (a) and (b) Output waveforms of Nb- and Al-contact JJ-FET
inverters, respectively, without VCLK. (c) and (d) Output waveforms with
VCLK switching from low to high at the VIN rising edge. (e) and (f) Output
waveforms with VCLK switching from low to high at the VIN falling edge.
VCLK is indicated in blue curves in (c)–(f). The other parameters are the
same as those used in Fig. 7.
Indeed, since the logic value of VOUT must be evaluated
when VCLK = 0, the waveform half-period should exceed
tPW + tr + tH, where tH is the hold time. It is noteworthy
that VCLK may be synchronized with the clock in a dynamic
logic gate.
IV. DISCUSSION
The model we employ in this article ignores the mesoscopic
effects and applies to ideal contacts. It is, therefore, necessary
to examine the validity of our assumptions. First, mesoscopic
effects can potentially change the IJ value. For example, while
Kondo resonances can suppress this magnitude, we expect a
minimal effect for the device in the short ballistic regime [21].
The experimentally observed V0 value is close to the ballistic
limit pi [11], suggesting that the JJ-FET is not operating
in the Kondo effect-dominated regime. Second, mesoscopic
effects can change the dependence of IJ on ϕ(t). Fortunately,
this current-phase relation remains sinusoidal for a short
ballistic junction in nanoscale [22]. On the other hand, in
a realistic device, carriers will observe a tunnel barrier at
the channel/contact interface, a key ingredient to validate the
sinusoidal current-phase relation [23]. It is noteworthy that
the current magnitude is similar to the case where there is no
tunnel barrier, since the reduction of current due to normal
reflections at the disordered junction is compensated by the
current increase from Andreev reflections [24]. We, therefore,
assess that a realistic JJ-FET with finite transparency between
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WEN et al.: JJ-FETs FOR BOOLEAN LOGIC CRYOGENIC APPLICATIONS 5373
the channel and contacts can still achieve V0 at the short
ballistic limit.
Additionally, in our analysis throughout, we have assumed
the JJ-FET gate overdrive VG − VT controls the gate charge
(qG) and therefore IC by modulating the weak link in the
channel. However, this unidirectional JJ-FET model where IDS
is set by qG without a back reaction is thermodynamically
unsound [25]. The energy of a JJ-FET is
E J F = q
2
G
2W LCG
+
2e
IC(qG)(1− cos ϕ(t)) (12)
where IC(qG) is IC with gate charge qG. Since VG − VT =
∂ EJF/∂qG, we find qG is reduced, compared to the unidirec-
tional model
qG = W LCG(V G − VT)−β(qG)2e (1− cos ϕ(t)) (13)
where β(qG) is β with gate charge qG. The back reaction
is negligible when the RHS second term is small, namely
γ = β(qG)/2eW LCG(VG−VT) 1, a condition which does
not hold for the logic device operation regime discussed here.
For the parameters used in the Nb-contact JJ-FET inverter at
zero VIN, i.e., VG−VT = 1.2 mV, W = 1 µm, and L = 50 nm,
the two terms of (13) RHS are comparable.
We note that β decreases with increasing VG−VT; hence, the
back reaction becomes particularly important when VIN is low.
This implies that if we ignore the back reaction, the channel
can be fully depleted and VOUT will be in an undefined
state. The back reaction can be compensated by shifting VT
to a more negative value. For example, the operation of an
Nb-contact JJ-FET inverter is restored by setting VT = −3.5
mV. While the back reaction adds extra complexity to the
design of JJ-FET logic gates, if it is properly compensated
at zero VIN, at high VIN, its impact is reduced.
It is of interest to investigate how advances in nanofabrica-
tion will influence the JJ-FET logic gates. Transistor scaling
effectively produces smaller L and larger CG. In order to val-
idate the model used in this article, L needs to be sufficiently
short compared to the superconducting coherence length
ξ0 = vF
pie
=
2√2piCG(VG − VT)
m∗pie3/2
(14)
where vF and m∗ are the Fermi velocity and effective electron
mass in the semiconductor channel, which are crucial to
achieve a significant ξ0 at the low VG −VT required by JJ-FET
logic gates. A large CG in the scaled JJ-FET device promises
a long ξ0 and small γ . Alternatively, it may also allow a
lower VG − VT to reduce power consumption. However, Q
will increase consequently, which imposes a design tradeoff
of CG and potentially justifies the necessity of VCLK.
The choice of superconductor contacts is another important
factor. Choosing a low contact has various benefits. In light
of the requirements of finite VG − VT for reasonable γ, ξ0,
and Q, and appreciable αR for signal restoration, we usually
have VG − VT ∼ . Then, we can approximate the power
consumption P ∝ ICV0 ∝ 5/2 and power-delay product
PτRL ∝ 3/2, indicating that smaller yields more efficient
JJ-FET logic gates. Additionally, we have Q ∝ √ and
ξ0 ∝ 1/
√
, promoting the overdamped operation and
relaxing the requirement of reduced L and m∗. However,
we also have γ ∝ 1/√, which indicates a low JJ-FET is
less immune to the back reaction. Also, a larger is favored
for faster speed given τRL ∝ 1/. The above arguments
impose a design tradeoff for .
Although JJ-FET logic gates cannot relax the requirement
of ultraprecise control of VT compared with cryogenic CMOS,
they provide a better circuit tolerance in the sense that JJ-FETs
are always in the ON state while a CMOS device has to make
a transition between ON and OFF states within the operating
voltage window. Moreover, the speed of the JJ-FET logic
gate is limited by τRL if designed properly for overdamped
operation, as opposed to the RC time constant in a CMOS
device, which can be unacceptably high for the low carrier
concentrations due to small VDD at cryogenic temperature.
On the other hand, JJ-FET logic gates possess a smaller
break-even operating voltage than cryogenic CMOS if we
factor in the static power consumption. JJ-FET logic gates
also demonstrate great compatibility with emerging material
platforms, e.g., the III–V quantum-well JJ-FET is a depletion-
mode n-type device [11]; the graphene channel can reach its
charge neutrality point at a slightly negative VG [10] and the
proposed JJ-FET logic gates can circumvent the issue of low
ON–OFF ratio for CMOS [26], [27]. Moreover, the low m∗ and
high vF in III–V quantum-well, and especially in graphene,
mitigate the conflict between long ξ0 and low VG − VT, e.g.,
Dirac electrons in graphene have an ξ0 = 70 and 470 nm in
Nb- and Al-contact JJ-FETs [28], respectively.
V. CONCLUSION
When cooling costs are factored in, the operating voltage of
CMOS-based circuits has to be scaled down significantly for
cryogenic computing to provide a net power reduction. JJ-FET
Boolean logic can harness the superconducting property of
these devices at these cryogenic temperatures and provide low
operating voltage on the order of superconductor gap voltage.
Assuming a short ballistic transport length, we employ the
static and RCSJ model to capture the behavior of JJ-FET
logic gates with fan-out. A global clock can mitigate the
underdamped operation, if necessary. Transistor scaling and
the choice of different superconducting contacts have notable
impacts on the device operation. For example, reduced
gate dielectric thickness guarantees better back-reaction
immunity but favors underdamped operation, and larger gap
voltage ensures a faster operation speed but at the cost of
reduced coherence length, hence channel length. We find
JJ-FET logic gates can be a promising candidate for dynamic
logic elements with ultrashort fall times and can utilize the
advantages of emerging channel materials like III–V quantum
wells and graphene.
ACKNOWLEDGMENT
The authors would like to thank S. K. Banerjee and
R. Pillarisetty for discussions.
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