ECE 4420 August 27, 2021 Fall 2021 Howard Luong Analog Integrated-Circuit Design and Analysis HOMEWORK #1 (DUE DATE: SEPTEMBER 27TH VIA CANVAS) 1. Download from the class web page the SPICE model parameters for the 0.35-µm and 0.18-µm TSMC CMOS processes. a. For an NMOS transistor with the W/L aspect ratio of 17.5µ/0.35µ, using the 0.35-µm model to: i. Obtain the IV dc characteristic curves (ID vs. VDS) ii. Obtain the circuit parameters µCox, VT, and body effect coefficient γ iii. Estimate the channel-length modulation parameter λ at a drain current of ~100 µA. iv. Estimate the transition frequency fT at a drain current of ~100 µA. b. Repeat (a) using the 0.18-µm model for two NMOS devices, one with the same aspect ratio of 17.5µm/0.35µm, and one with the aspect ratio of 9.0µm/0.18µm. c. Compare the results obtained from (a) and (b) and comment on the differences. A table of comparison for the circuit parameters obtained in Parts ii-iv would be useful. Draw some conclusions regarding process and model choices for optimal design. 2. Design a differential NMOS amplifier with resistive loads that has a low-frequency voltage gain of 10dB. Use a supply voltage of 2.5 V and maximum dc power consumption of 1 mW. Note that you may want to use channel lengths larger than the minimum to increase the transistors’ output resistance and thus the gain. a. Assume that the 0.35-µm process and the parameters obtained from Problem 1(a) are used. Calculate the W/L of the input NMOS transistors and the resistive loads RL required. b. Assume now that the 0.18-µm process and its associated parameters obtained from Problem 1(b) are used. Recalculate the W/L of the input transistors and the resistive loads RL. c. Simulate the designs in (a) and (b) using appropriate models. Compare and comment on the results and justify any difference.