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程序代写案例-COMP12111 MU0
时间：2021-11-16
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COMP12111: Fundamentals of Computer Engineering
MU0 Overview
The following provides a brief overview of the MU0 processor and its operation with respect to completing the laboratory exercises. More information can be found in the course unit material, which you should refer to.
The Processor Interface The input and output signals to the processor are defined as the interface, these are the signals that connect the processor to the outside world. The microprocessor has a limited, well-defined interface, as shown in Figure 1, with the following signals:
§ Clk: input clock to the processor
§ Reset: input indicating that the processor should adopt a predefined initial state
§ Address bus: 12-bit output to memory
§ Data_out bus: 16-bit output to memory
§ Data_in bus: 16-bit input from memory
§ Rd: output that is asserted when the memory should be read
§ Wr: output that is asserted when the memory should be written
§ Halted: output indicating the processor has halted (optional) We can also see in Figure 1 that internally, MU0 is split into datapath and control modules, as it is a sequential system. We will revisit these elements later.
Figure 1: MU0 Interface The programmers’ model for MU0 has two registers as illustrated in Figure 2:
§ a 16-bit Accumulator, Acc
§ a 12-bit Program Counter, PC
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The 16-bit instruction format consists of a 4-bit code representing the instruction, F, and a 12-bit value representing an address, S, as illustrated in Figure 2.
Figure 2: MU0 Registers & Instruction Format
A list of available instructions is given in Figure 3. The instructions act on values (or operands) held (stored) in memory or held in the accumulator register.
F Mnemonic Function 0000 LDA S Load accumulator from memory location S 0001 STA S Store accumulator to memory location S 0010 ADD S Add memory location S to accumulator 0011 SUB S Subtract memory location S from accumulator 0100 JMP S Jump to instruction address S 0101 JGE S Jump to instruction address S if accumulator is +ive 0110 JNE S Jump to instruction address S if accumulator is not 0 0111 STP Halt execution – Halted signal goes high 1000 -1111 - Reserved, currently unused
Figure 3: MU0 instructions
In the case of reset being asserted, the internal state of the processor registers are set to 0, resulting in the PC pointing at address 000 in memory, so execution will start again by fetching the instruction stored at address 000 – so this is where the first instruction should reside in memory.
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Memory interface To initiate memory access there are two memory control signals defined in the interface to MU0:
• Wr – write control - if the processor asserts the write control signal, the data on the Data_out bus will be stored at the memory address that the processor places on the Address bus.
• Rd – read control - if the processor asserts the read control signal, the data stored at the memory address placed on the Address bus will be returned on the Data_in bus. Wr and Rd are mutually exclusive - they cannot go high at the same time - as this wouldn’t make sense, as you cannot both write to and read from memory at the same time (well not with the memory model adopted for MU0!)
Control The “control” basically controls the operation of the processor. As the processor is a sequential system then the control contains the finite state machine – the heart of any sequential system. The control tells the “datapath” part of the processor – the element that processes the data - what to do depending on what state we are in (in the case of MU0: fetch or decode/execute) and what instruction is being executed. The control block for MU0 can be split into two elements, a finite state machine (FSM) and a control signal decode block that, depending upon the current state of the FSM and the current instruction being executed, determines the state of the signals that control the operation of the datapath shown.
Figure 4: MU0 Control block
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MU0 has a simple FSM as shown in the state transition diagram in Figure 5, which alternates between the Fetch and Decode/Execute (we will just call this execute from now on) states unless the processor is halted (due to a STP instruction being executed). The execution of an instruction is a two-stage process starting with the fetch phase, during with the processor fetches the instruction from the memory using the address held in the PC, plus PC increment. This is then followed by the execute phase where the fetched instruction is then decoded (by the control block) and the instruction
executed. During the fetch phase the PC is incremented (PC + 1) to point at the next instruction to be executed. If a branch is taken, then the PC will be overwritten with a new address during the decode/execute phase. The fetched instruction is placed in a special register called the instruction register (IR) (which the programmer does not see) where it is decoded to determine what operation is required, and on what data, during the execute phase.
Figure 5: MU0 control state transition diagram
The control logic requires the following inputs:
§ Clk : global external clock
§ Reset : system reset
§ F<3:0> : the upper 4 bits of the fetched instruction - IR[15:12] - decoded in the control unit to determine the required operation in the datapath.
§ N : the Negative flag (high when the accumulator content is negative), which is used when evaluating conditional branches.
§ Z : the Zero flag, (high when the accumulator content is zero), which is used when evaluating conditional branches. Depending on the current state of the FSM the control logic will configure the following control signals to the processor datapath depending on the state of the FSM (fetch or execute) and the instruction being executed:
§ PC_En : Programme Counter write enable – enables the PC to be overwritten on the next positive edge on the clock when taken high.
§ Acc_En : Accumulator write enable – enables the Acc to be overwritten on the next positive edge on the clock when taken high.
§ IR_En : Instruction Register write enable – enables the IR to be overwritten on the next positive edge on the clock when taken
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high.
§ X_sel, Y_sel : select signals for the ALU input MUXs - determines where the inputs to the ALU come from.
§ Addr_sel : Address output MUX select – determines where the address data comes from.
§ M<1:0> : Determines the ALU function
§ Halted : when high the processor is halted in the halted state As the FSM only has two states, then the state code is only 1 bit, hence Fetch is 0, and Execute is 1.
MU0 Arithmetic Logic Unit (ALU) The MU0 ALU performs a number of arithmetic functions depending on the value of the 2-bit control signal M. These operations act on the two inputs to the ALU: X and Y, as shown in Figure 6. M Operation 00 Y Passthrough Y input 01 X+Y Addition 10 X+1 Increment X 11 X-Y Subtraction
Figure 6: ALU operations as a function of M So, for example, when processing an ADD instruction, a value of M=01 instructs the ALU to perform ADD operation, a value of M=11 instructs the ALU to perform a Sub operation etc. It is important to acknowledge that the ALU is used in the Fetch phase to perform the +1 operation, in which case M = 10.
MU0 Datapath Figure 7 illustrates one possible implementation of the MU0 datapath, along with the key control signals that control the operation of the various components of the datapath. The updates of the registers, PC_En for the PC, IR_En for the IR and Acc_En for the Acc, are used to control when the registers are updated as we do not want them to be updated on every rising edge of the clock. Data movement through the datapath is controlled using three multiplexers, which do the following:
• X_sel selects between the accumulator (ACC) and program counter (PC) to form the X_input to the ALU – 16-bit input/output.
• Addr_sel selects between PC and the address section of the instruction register to form the address to memory – 12-bit input/output.
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• Y_sel selects between the data to the ALU or the address section of the instruction register (IR) to form the Y_input to the ALU – 16-bit input/output. As the address bus is 12 bits and the data bus 16 bits, then we have a mixture of 12 and 16-bit buses in the MU0 datapath. As the PC is 12 bits, then we have to extend this to 16 bits before it can be passed through the X_sel MUX, consequently we must prepend 4’b000 to the value of PC before the input to the MUX – you can see how this is achieved in the MU0 datapath schematic. The operation of the MUXs is determined by the current state of the FSM, as well as the type of instruction during the decode/execute phase – you can determine this by considering the movement of data through the datapath during the instruction execution in the fetch and execute phases, as described below. Figure 8 gives some detail of the state of these control signals as a function of the current state of the FSM and the instruction. Y_sel and Addr_sel have deliberately left incomplete, apart from the fetch phase, because this is for you to determine for exercise 3.
Figure 7: MU0 datapath
Fetch phase What do we set the control signals to during the fetch phase? The PC holds the address of the next instruction in memory. In the fetch phase the memory address held in the PC must be placed on the address bus so that the data from memory (the instruction) is read into the IR. So addr_sel must select the value from the PC to be placed on the address bus in the fetch phase. The value in the PC is incremented by applying the value in the PC to the X-input to the ALU and performing a +1 operation (M = 10). So, X_sel must select the PC during this
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phase. As the Y-input to the ALU is not used during an instruction fetch, then we do not need to worry what Y_sel is set to. In the case of the register enable signals, PC_En, Acc_En and IR_En, we need to identify which of these registers needs updating in the fetch phase. If we are to update then we set the enable signal to 1, if not, then we must set the enable signal to 0. So, in fetch we are doing two things: getting the instruction and placing this in the IR register and updating the PC to point to the next instruction address in memory. We aren’t updating the contents of the accumulator register. Consequently, we must set PC_En = 1, IR_En = 1 and Acc_En = 0.
state IR[15:12] Instr X_sel Y_sel Addr_sel 0 xxxx xxx 1 x 0 1 0000 LDA x ? ? 1 0001 STA 0 ? ? 1 0010 ADD 0 ? ? 1 0011 SUB 0 ? ? 1 0100 JMP x ? ? 1 0101 JGE x ? ? 1 0110 JNE x ? ? 1 0111 STP x ? ? 1 1xxx x x x x
Figure 8: MU0 State Transition Table
Decode/execute During the decode/execute phase the operation of the datapath depends upon the instruction fetched. The values of the control signals Addr_sel and Y_sel, depend on the type of instruction being executed. We can see from Figure 6 that during the Fetch phase, we need to pass the value through XMux and round to the X-input of the ALU, so we can perform an increment operation, so X_sel = 1. In the case of the decode/execute phase, the value of X_sel is independent of the instruction and should be set to 0. In some case, LD and branch instructions XMux isn’t used, so we could set to X. In the case of Addr_sel – in fetch we need to pass the address from the PC to memory, so the address bus is connected to the PC and Addr_sel = 0. During the instruction decode/execute phase any data placed on the address comes from the IR, as the address portion of the instruction (least significant 12 bits) provides the address of the data to be operated on, which gives you an indication of where the address should come from.
YMux isn’t used in the Fetch phase (no data is passed to the Y-input of the ALU) so we can set Y_sel to X. However, in the decode/execute phase the value of Y_sel depends on the instruction. In the case of all instructions apart from branch instructions the data to the Y-input of the ALU must come from memory – as here we are operating on data from memory for these instructions. However, in the case of branch instructions (Jxx) the data to the Y-input of the ALU comes from the instruction, which is the least significant 12 bits of the IR, as it is the address of the new instruction (to go into the PC) if the branch is to be taken.
学霸联盟
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COMP12111: Fundamentals of Computer Engineering
MU0 Overview
The following provides a brief overview of the MU0 processor and its operation with respect to completing the laboratory exercises. More information can be found in the course unit material, which you should refer to.
The Processor Interface The input and output signals to the processor are defined as the interface, these are the signals that connect the processor to the outside world. The microprocessor has a limited, well-defined interface, as shown in Figure 1, with the following signals:
§ Clk: input clock to the processor
§ Reset: input indicating that the processor should adopt a predefined initial state
§ Address bus: 12-bit output to memory
§ Data_out bus: 16-bit output to memory
§ Data_in bus: 16-bit input from memory
§ Rd: output that is asserted when the memory should be read
§ Wr: output that is asserted when the memory should be written
§ Halted: output indicating the processor has halted (optional) We can also see in Figure 1 that internally, MU0 is split into datapath and control modules, as it is a sequential system. We will revisit these elements later.
Figure 1: MU0 Interface The programmers’ model for MU0 has two registers as illustrated in Figure 2:
§ a 16-bit Accumulator, Acc
§ a 12-bit Program Counter, PC
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The 16-bit instruction format consists of a 4-bit code representing the instruction, F, and a 12-bit value representing an address, S, as illustrated in Figure 2.
Figure 2: MU0 Registers & Instruction Format
A list of available instructions is given in Figure 3. The instructions act on values (or operands) held (stored) in memory or held in the accumulator register.
F Mnemonic Function 0000 LDA S Load accumulator from memory location S 0001 STA S Store accumulator to memory location S 0010 ADD S Add memory location S to accumulator 0011 SUB S Subtract memory location S from accumulator 0100 JMP S Jump to instruction address S 0101 JGE S Jump to instruction address S if accumulator is +ive 0110 JNE S Jump to instruction address S if accumulator is not 0 0111 STP Halt execution – Halted signal goes high 1000 -1111 - Reserved, currently unused
Figure 3: MU0 instructions
In the case of reset being asserted, the internal state of the processor registers are set to 0, resulting in the PC pointing at address 000 in memory, so execution will start again by fetching the instruction stored at address 000 – so this is where the first instruction should reside in memory.
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Memory interface To initiate memory access there are two memory control signals defined in the interface to MU0:
• Wr – write control - if the processor asserts the write control signal, the data on the Data_out bus will be stored at the memory address that the processor places on the Address bus.
• Rd – read control - if the processor asserts the read control signal, the data stored at the memory address placed on the Address bus will be returned on the Data_in bus. Wr and Rd are mutually exclusive - they cannot go high at the same time - as this wouldn’t make sense, as you cannot both write to and read from memory at the same time (well not with the memory model adopted for MU0!)
Control The “control” basically controls the operation of the processor. As the processor is a sequential system then the control contains the finite state machine – the heart of any sequential system. The control tells the “datapath” part of the processor – the element that processes the data - what to do depending on what state we are in (in the case of MU0: fetch or decode/execute) and what instruction is being executed. The control block for MU0 can be split into two elements, a finite state machine (FSM) and a control signal decode block that, depending upon the current state of the FSM and the current instruction being executed, determines the state of the signals that control the operation of the datapath shown.
Figure 4: MU0 Control block
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MU0 has a simple FSM as shown in the state transition diagram in Figure 5, which alternates between the Fetch and Decode/Execute (we will just call this execute from now on) states unless the processor is halted (due to a STP instruction being executed). The execution of an instruction is a two-stage process starting with the fetch phase, during with the processor fetches the instruction from the memory using the address held in the PC, plus PC increment. This is then followed by the execute phase where the fetched instruction is then decoded (by the control block) and the instruction
executed. During the fetch phase the PC is incremented (PC + 1) to point at the next instruction to be executed. If a branch is taken, then the PC will be overwritten with a new address during the decode/execute phase. The fetched instruction is placed in a special register called the instruction register (IR) (which the programmer does not see) where it is decoded to determine what operation is required, and on what data, during the execute phase.
Figure 5: MU0 control state transition diagram
The control logic requires the following inputs:
§ Clk : global external clock
§ Reset : system reset
§ F<3:0> : the upper 4 bits of the fetched instruction - IR[15:12] - decoded in the control unit to determine the required operation in the datapath.
§ N : the Negative flag (high when the accumulator content is negative), which is used when evaluating conditional branches.
§ Z : the Zero flag, (high when the accumulator content is zero), which is used when evaluating conditional branches. Depending on the current state of the FSM the control logic will configure the following control signals to the processor datapath depending on the state of the FSM (fetch or execute) and the instruction being executed:
§ PC_En : Programme Counter write enable – enables the PC to be overwritten on the next positive edge on the clock when taken high.
§ Acc_En : Accumulator write enable – enables the Acc to be overwritten on the next positive edge on the clock when taken high.
§ IR_En : Instruction Register write enable – enables the IR to be overwritten on the next positive edge on the clock when taken
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high.
§ X_sel, Y_sel : select signals for the ALU input MUXs - determines where the inputs to the ALU come from.
§ Addr_sel : Address output MUX select – determines where the address data comes from.
§ M<1:0> : Determines the ALU function
§ Halted : when high the processor is halted in the halted state As the FSM only has two states, then the state code is only 1 bit, hence Fetch is 0, and Execute is 1.
MU0 Arithmetic Logic Unit (ALU) The MU0 ALU performs a number of arithmetic functions depending on the value of the 2-bit control signal M. These operations act on the two inputs to the ALU: X and Y, as shown in Figure 6. M Operation 00 Y Passthrough Y input 01 X+Y Addition 10 X+1 Increment X 11 X-Y Subtraction
Figure 6: ALU operations as a function of M So, for example, when processing an ADD instruction, a value of M=01 instructs the ALU to perform ADD operation, a value of M=11 instructs the ALU to perform a Sub operation etc. It is important to acknowledge that the ALU is used in the Fetch phase to perform the +1 operation, in which case M = 10.
MU0 Datapath Figure 7 illustrates one possible implementation of the MU0 datapath, along with the key control signals that control the operation of the various components of the datapath. The updates of the registers, PC_En for the PC, IR_En for the IR and Acc_En for the Acc, are used to control when the registers are updated as we do not want them to be updated on every rising edge of the clock. Data movement through the datapath is controlled using three multiplexers, which do the following:
• X_sel selects between the accumulator (ACC) and program counter (PC) to form the X_input to the ALU – 16-bit input/output.
• Addr_sel selects between PC and the address section of the instruction register to form the address to memory – 12-bit input/output.
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• Y_sel selects between the data to the ALU or the address section of the instruction register (IR) to form the Y_input to the ALU – 16-bit input/output. As the address bus is 12 bits and the data bus 16 bits, then we have a mixture of 12 and 16-bit buses in the MU0 datapath. As the PC is 12 bits, then we have to extend this to 16 bits before it can be passed through the X_sel MUX, consequently we must prepend 4’b000 to the value of PC before the input to the MUX – you can see how this is achieved in the MU0 datapath schematic. The operation of the MUXs is determined by the current state of the FSM, as well as the type of instruction during the decode/execute phase – you can determine this by considering the movement of data through the datapath during the instruction execution in the fetch and execute phases, as described below. Figure 8 gives some detail of the state of these control signals as a function of the current state of the FSM and the instruction. Y_sel and Addr_sel have deliberately left incomplete, apart from the fetch phase, because this is for you to determine for exercise 3.
Figure 7: MU0 datapath
Fetch phase What do we set the control signals to during the fetch phase? The PC holds the address of the next instruction in memory. In the fetch phase the memory address held in the PC must be placed on the address bus so that the data from memory (the instruction) is read into the IR. So addr_sel must select the value from the PC to be placed on the address bus in the fetch phase. The value in the PC is incremented by applying the value in the PC to the X-input to the ALU and performing a +1 operation (M = 10). So, X_sel must select the PC during this
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phase. As the Y-input to the ALU is not used during an instruction fetch, then we do not need to worry what Y_sel is set to. In the case of the register enable signals, PC_En, Acc_En and IR_En, we need to identify which of these registers needs updating in the fetch phase. If we are to update then we set the enable signal to 1, if not, then we must set the enable signal to 0. So, in fetch we are doing two things: getting the instruction and placing this in the IR register and updating the PC to point to the next instruction address in memory. We aren’t updating the contents of the accumulator register. Consequently, we must set PC_En = 1, IR_En = 1 and Acc_En = 0.
state IR[15:12] Instr X_sel Y_sel Addr_sel 0 xxxx xxx 1 x 0 1 0000 LDA x ? ? 1 0001 STA 0 ? ? 1 0010 ADD 0 ? ? 1 0011 SUB 0 ? ? 1 0100 JMP x ? ? 1 0101 JGE x ? ? 1 0110 JNE x ? ? 1 0111 STP x ? ? 1 1xxx x x x x
Figure 8: MU0 State Transition Table
Decode/execute During the decode/execute phase the operation of the datapath depends upon the instruction fetched. The values of the control signals Addr_sel and Y_sel, depend on the type of instruction being executed. We can see from Figure 6 that during the Fetch phase, we need to pass the value through XMux and round to the X-input of the ALU, so we can perform an increment operation, so X_sel = 1. In the case of the decode/execute phase, the value of X_sel is independent of the instruction and should be set to 0. In some case, LD and branch instructions XMux isn’t used, so we could set to X. In the case of Addr_sel – in fetch we need to pass the address from the PC to memory, so the address bus is connected to the PC and Addr_sel = 0. During the instruction decode/execute phase any data placed on the address comes from the IR, as the address portion of the instruction (least significant 12 bits) provides the address of the data to be operated on, which gives you an indication of where the address should come from.
YMux isn’t used in the Fetch phase (no data is passed to the Y-input of the ALU) so we can set Y_sel to X. However, in the decode/execute phase the value of Y_sel depends on the instruction. In the case of all instructions apart from branch instructions the data to the Y-input of the ALU must come from memory – as here we are operating on data from memory for these instructions. However, in the case of branch instructions (Jxx) the data to the Y-input of the ALU comes from the instruction, which is the least significant 12 bits of the IR, as it is the address of the new instruction (to go into the PC) if the branch is to be taken.
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