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Page 1 of 5


UNIVERSITY OF GLASGOW

Degrees of MEng, BEng, MSc and BSc in Engineering

VLSI DESIGN 4/M (ENG4138/ENG5092)
Friday 19 December 2014
13:00-15:00
Answer FOUR questions
Answer only TWO questions from each of sections A and B

Each question is worth 25 marks

The numbers in square brackets in the right-hand margin indicate the marks allotted to the
part of the question against which the mark is shown. These marks are for guidance only.
An electronic calculator may be used provided that it does not have a facility for either
textual storage or display, or for graphical display.
If a calculator is used, intermediate steps in the calculation should be indicated.
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SECTION A: Attempt any TWO questions [50 marks]
Q1 (a) Sketch a transistor circuit for a CMOS inverter, including a parasitic load
capacitance (CL), labeling its input, output and supply voltage connections. [5]
(b) The input is subjected to a square edge transition from input LOW to input
HIGH at a time t0. Sketch a timing diagram for the input and output waveforms
illustrating output voltage value and corresponding times on the plot. [5]
(c) Using the answer for part (b) of this question, annotate the timing diagram with
operating mode of both the NMOS and PMOS transistors, and the portion of
the time axis for which the transistor modes you identify apply. [5]
(d) Using the timing diagram you have produced in parts (b) and (c) of this
question, and the charging equation for a capacitor, show that the fall time for
the voltage at the output of a CMOS inverter is given by:
t f =
knCL
bnVDD

where kn is a constant and all the other symbols have their usual meaning. [10]

Q2 a) Sketch the circuit diagram for a CMOS standard cell with the function:
Z = (A ×B+C) ×D [8]
(b) Transistor sizing (T-sizing) is used to optimize the performance of standard
cells. The design is based on a standard cell library with a “unit” inverter with
Wn = Wni, and Wp = Wpi. The ratio Wpi/Wni = 2.
(i) Analyse the circuit you drew in part (a) to determine the stack depth of
each block of transistors. [6]
(ii) T-size the circuit of part (a) to match the inverter’ output characteristics
assuming a linear T-sizing method is used. State any design choices
that you make to arrive at a solution. [8]
(iii) How would you modify the T-size calculation if the Fan-Out were to
be doubled? [3]
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Page 3 of 5

Q3 (a) A pipelined system architecture is required to have the ability to arbitrarily shift
data bits either to the left or the right, or not at all, in a single clock cycle. Sketch,
using pass-transistor logic, a circuit that will do this. You may assume that there
is an input and an output register associated with the device. [8]
(b) A simple digital multiplier relies on a process of successive shifting of data to
the left, and addition.
(i) Show how you can express a m-bit unsigned binary number using radix-
2 notation. [4]
(ii) By expressing two unsigned binary numbers X and Y, of length m and n
respectively, in radix-2 notation, derive a formula for the product Z =
XY. [8]
(c) Using your answer for part (b) of this question, write down the Boolean
expression for the partial product that would appear in a logical implementation
of the multiplier, and sketch the logic circuit, using conventional symbols, that
would provide the required function. [5]


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Page 4 of 5

SECTION B: Attempt any TWO questions [50 marks]
Q4 (a) Draw the schematic of a simple CMOS current mirror employing p-channel
transistors and explain its operation. [6]
(b) State the advantages of using a current mirror as an active load in integrated
amplifier circuits. [3]
(c) A two-stage architecture is one of the most basic approaches for realising a
CMOS operational amplifiers (Op-amp).
(i) Draw a clearly labeled schematic diagram of this type of Op-amp. [6]
(ii) Identify and briefly explain the functions of each stage of your
circuit. [7]
(iii) Identify each current mirror in your circuit, stating its role in each case.
[3]

Q5 (a) A popular digital-to-analogue converter (DAC) architecture, the potentiometric
DAC, is based on selecting one tap of a segmented resistor string by a switch
network.
(i) Draw the circuit diagram of a 2-bit potentiometric DAC. [4]
(ii) State the 3 main advantages of this type of DAC. What is its main
disadvantage? [4]
(iii) Hence or otherwise, explain how this DAC architecture is exploited in
high resolution converters. [2]
(b) Another popular DAC architecture is based on the resistor-ladder (R-2R)
network. Draw the circuit diagram for a 3-bit R-2R based DAC. [5]
(c) By analysis of the circuit of Q5(b) show mathematically how the input bits of
the DAC relate to the analogue output voltage. [6]
(d) What are the advantages and disadvantages of the R-2R DAC when compared
to other DAC architectures (excluding the potentiometric DAC)? [4]
End of question paper
Page 5 of 5

Q6 (a) A dc voltage of 2 V is applied to the input of the switched-capacitor circuit of
Figure Q6 in which C1 is 10 pF. If a clock frequency of 200 kHz is used:
(i) What charge is transferred for each cycle of the two-phase clock, having
the high ( ) clock and the low ( ) clock phases? [3]
(ii) What is the average current drawn from the input source? [3]
(iii) What is the equivalent input resistance? [3]
(iv) What would be the equivalent resistance if C1 were 200 pF? [3]
(b) The integrator function in a sigma-delta (-) analogue-to-digital converter
(ADC) is realized using switched-capacitor (SC) techniques.
(i) Sketch the circuit diagram of a non-inverting SC integrator. [3]
(ii) List the advantages of SC integrators compared to conventional resistor-
capacitor integrators. [3]
(c) The signal-to-noise ratio of a first order - ADC is = 6.02(n + 1.5m) - 3.41 dB,
where the basic ADC is n-bit and the oversampling ratio is 2m. What sample
rate is required to obtain 16-bit resolution if the system uses a 1-bit ADC and
the Nyquist sampling rate is 25 kHz? [3]
(d) What are the main advantages of - ADCs? [4]

Figure Q6.


Vin
V0
C1
 
+
C2
+

OVER
Page 1 of 9
ENG4138 2014 SOLUTIONS
SECTION A: Attempt any TWO questions [50 marks]

Q1 (a) Sketch a transistor circuit for a CMOS inverter, including a parasitic load
capacitance (CL), labeling its input, output and supply voltage connections. [4]
Vin Vout
VDD
CL

(b) The input is subjected to a square edge transition from input LOW to input
HIGH at a time t0. Sketch a timing diagram for the input and output
waveforms indicating the 10 % and 90 % output voltage value and
corresponding times. [4]
V
t
0.9 VDD
0.1 VDD
Input
Step
Output
Slope
t0 t1 t2 t3
VDD - Vtn

(c) Using the answer for part (b) of this question, annotate the timing diagram
with operating mode of both the NMOS and PMOS transistors, and the
portion of the time axis for which the transistor modes you identify apply. [5]
Before t0, PMOS is in linear region, after t0, PMOS is cut-off.
Before t0, NMOS is cut-off. For t0 < t < t2, NMOS is saturated.
For t > t2, NMOS is in linear region.
(d) Using the timing diagram you have produced in parts (b) and (c) of this
question, and the charging equation for a capacitor, show that the fall time for
the voltage at the output of a CMOS inverter is given by:
OVER
Page 2 of 9
t f =
knCL
bnVDD

where kn is a constant and all the other symbols have their usual meaning. [12]

( )
( ) ( )
( )
( )
( )
DD
tn
n
DDn
Ln
DD
tnDD
tnDDn
L
tnDDn
DDtnL
V
V
n
n
n
n
n
k
V
Ck
V
VV
VV
C
VV
VVC
=
-
-
+
-
-
=
b
»÷÷
ø
ö
çç
è
æ -
-b
+
-b
-
=
and
1
2019ln
1
1.02
where
2019
ln
1.02
2
2

OVER
Page 3 of 9
a) Sketch the circuit diagram for a CMOS standard cell with the function:

Z = (A.B+C).D [8]

(b) Transistor sizing (T-sizing) is used to optimize the performance of standard
cells. The design is based on a standard cell library with a “unit” inverter with
Wn = Wni, and Wp = Wpi. The ratio Wpi/Wni = 2.
(i) Analyse the circuit you drew in part (a) to determine the stack depth
of each block of transistors. [6]
See table below.
(ii) T-size the circuit of part (a) to match the inverter’ output
characteristics assuming a linear T-sizing method is used. State any
design choices that you make to arrive at a solution. [8]

PMOS Blocks NMOS Blocks Stack depth (S) New Wp New Wn
A, B, C
D


A, B, D
C, D
2
1
3
2
2Wip = 4Win
Wip = 2Win


3Win
2Win
The two NMOS blocks both contain input D, hence there are two possible solutions for D.
An appropriate design choice is to make the C-NMOSFET the larger of the two possible
solutions (i.e. worst-case).
(iii) How would you modify the T-size calculation if the Fan-Out was
doubled? [3]
Double the size of every transistor in the cell.

OVER
Page 4 of 9
Q3 (a) A pipelined system architecture is required to have the ability to arbitrarily
shift data bits either to the left or the right, or not at all, in a single clock cycle.
Sketch, using pass-transistor logic, a circuit that will do this. You may assume
that there is an input and an output register associated with the device. [8]


(b) A simple digital multiplier relies on a process of successive shifting of data to
the left, and addition.
(i) Show how you can express a m-bit unsigned binary number using
radix-2 notation. [4]
jik
pyxP
yxPXY
yY
xX
nm
k
k
k
n
j
ji
ji
m
i
n
j
j
j
m
i
i
i
n
j
j
j
m
i
i
i
+=
==\
===
==
==
ååå
åå
å
å
-+
=
-
=
+
-
=
-
=
-
=
-
=
-
=
where
22
22product
2multiplier
2ndmultiplica
1
0
1
0
1
0
1
0
1
0
1
0
1
0

(ii) B expressing two unsigned binary numbers X and Y, of length m and
n respectively, in radix-2 notation, derive a formula for the product Z =
XY. [8]
OVER
Page 5 of 9
jik
pyxP
yxPXY
yY
xX
nm
k
k
k
n
j
ji
ji
m
i
n
j
j
j
m
i
i
i
n
j
j
j
m
i
i
i
+=
==\
===
==
==
ååå
åå
å
å
-+
=
-
=
+
-
=
-
=
-
=
-
=
-
=
where
22
22product
2multiplier
2ndmultiplica
1
0
1
0
1
0
1
0
1
0
1
0
1
0

(c) Using your answer for part (b) of this question, write down the Boolean
expression for the partial product that would appear in a logical
implementation of the multiplier, and sketch the logic circuit, using
conventional symbols, that would provide the required function. [5]

Each of the bit-wise only products xiyj that occurs in the double summation is
a partial product. Because the partial product is a bit-wise operation, the
function is simply P= X.Y. The student should therefore sketch the logic
symbol for an AND-gate only, Anything more complicated, even if it contains
an AND gate is wrong.
OVER
Page 6 of 9
ENG4138_2014_Section_B_Solutions

Q4
a)
IREF
IOUT
RREF
VDD
Q2
[4 marks]
If both transistors are the same size, fabricated next to each other and are in the active region,
they will have the same current since they both have the same gate voltage, i.e. IOUT = IREF/bias. [2
marks]

b) An active load realises a high-impedance load required for an amplifier (replaces large
resistors, or a large power supply voltage that would otherwise be required). [3 marks]

c) i)
Vout2
vin
- vin
+
Vbias
Q2 QC
CC
Q4
Q5
I = 100uDC
[6 marks]
(ii) The basic 2-stage Op-amp consists of:-
a) a differential input stage: in this case uses a p-channel input pair (transistors Q1 and Q2)
with an n-channel current mirror load; this stage (1) is for rejection of common-mode (noise)
signals
b) a second gain stage (an inverter): this is transistor Q5, also having an active load Q6; this
stage (2) is to provide high amplification.
c) Capacitor Cc and transistor Qc (acting as a voltage controlled resistor) are included for
Op-amp compensation to ensure stability when the Op-amp is used with feedback;
d) the biasing circuitry is realised using a current mirror, transistor Q8, together with
transistors Q7 and Q6. [7 marks]
OVER
Page 7 of 9

iii) Current mirrors:
Q3, Q4: active load
Q8, Q6: active load
Q8, Q7: bias (current) [3 marks]

Q5
a)
i)
+
vout
R b2
b1
R
R
R
Vref
[4 marks]
ii) Advantages:
- This DAC has guaranteed monotonicity, i.e. has a 1:1 correspondence between the digital
input (b1b2) and the analogue output (vout) despite any component (resistor) mismatches.
- This DAC can be used to interpolate between any two arbitrary voltages with a resolution of
2n steps
- Only one resistor value and MOSFETs are required for circuit implementation – accurate IC
realisation of the circuit is possible. [3 marks]
Disadvantage:
- Large number of resistors, 2n, required for an n-bit DAC [1 mark]
iii) Interpolation between any two arbitrary voltages (with a resolution of 2n steps) as well
guaranteed monotonicity makes it possible to realise high resolution converters. [2 marks]
b)
OVER
Page 8 of 9
+
b3b2b1
S3S2S1
IO
VO
RF
+
-
vref
i3i2i1
Iref
2R
R R
2R 2R
2R
[5 marks]
c)
R
V
i
ref
2
1  ;
R
Vi
i
ref
2
1
2
22
 ;
R
Vii
i
ref
3
12
3
242


The are either diverted to the ground bus (bi = 0) or to the virtual ground bus (bi = 1)

321 iiiIO 








3
3
2
21
222
bbb
R
R
VIRV FrefOFO
[6 marks]
d) Adv.: with a 2:1 resistance spread, R-2R DACs can be fabricated monolithically to a high
degree of accuracy.
Disad.:R-2R resistor mismatch in MSB positions can impact DAC linearity. [4 marks]

Q6
(a)
(i) With C1 connected to Vin ( clock phase), it charges to Q = C1Vin. This charge
is transferred to C2 on the  clock phase
CVCQ in
11
1 102
 [3 marks]

(ii) AAQfI cavg 4104102010200
6123   [3 marks]

(iii) 11VCfI cavg , therefore
1
1 1
CfI
V
R
cavg
eq 

for C1 = 10 pF, 





MReq 5.0
102
1
101010200
1
6123
[3 marks]

(iv) For C1 = 200 pF, 





kReq 250
104
1
1020010200
1
5123
[3 marks]

b) i)
END
Page 9 of 9

+Vin
b)
V0
C1
+
C2
[3 marks]
ii) no resistors; cutoff frequeny (0) defined by capacitance ratios (easier to control and
maintain); & 0 is proportional to clock frequency. [3 marks]

c) n = 1; 1+1.5m = 16 or m = 10.
Oversampling ratio, k = 2m =210 = 1024
Oversampling rate = kfs = 102425 kHz = 25.6 MHz [3 marks]
d)
- minimises quantization noise (high SNR); linearity of 1-bit DAC; simplifies required
analogue circuitry, e.g. no anti-aliasing filter required, only 1-bit ADC and DAC required, [4