A Broadband Variable Gain Low Noise Amplifier Covering 28/38 GHz
bands with Low Phase Variation in 90-nm CMOS
for 5G Communications
Kai-Chun Chang1, Yunshan Wang, and Huei Wang2
Department of Electrical Engineering and Graduate Institute of Communication Engineering,
National Taiwan University, Taipei 106, Taiwan
1r08942014@ntu.edu.tw, 2hueiwang@ntu.edu.tw

Abstract—This paper presents a broadband, variable gain low
noise amplifier (VGLNA) with low phase variation in 90-nm
CMOS technology. The cascaded PMOS gain-boosting current
steering VGA and a modified current steering VGA with the
inductive phase-inversion network is utilized to compensate
phase variation within the gain control range (GCR). In order to
enhance overall gain of the circuit, gm-boosting and single-ended
neutralization techniques are applied to the circuit. The VGLNA
exhibits a peak gain of 21.4 dB at 37 GHz, 3-dB bandwidth
covering from 26 to 30.5 GHz (band1) and 33.8 to 40.6 GHz
(band2), respectively. An RMS phase error less than 4.3° and the
maximum phase variation of 7.2° are achieved within the 9.8-dB
gain control range (GCR) in the 3-dB bandwidth. The noise
figure is 4.7 dB at 36 GHz in the maximum gain state. The chip
consumes 17.9 mW dc power from 1-V voltage supply. To the
author’s knowledge, this circuit shows the highest figure-of-merit
(FOM) among previous published CMOS VGAs with low phase
variation design.
Keywords—variable gain amplifier (VGA), current-steering,
phase compensation, low phase variation, millimeter-wave
(mmW), phased-array.
I. INTRODUCTION
With the explosively growing demand for high-data-rate
applications, the phase-array system plays an important role in
millimeter-wave 5G systems. VGA is one of the key
components in the mmW phased-arrays for 5G applications.
Besides the gain-control function, the phase variations in
different gain states should be minimized to ease the
calibration of the phased-array.
To achieve wideband low phase variation, some advanced
techniques were reported in [1], [2]. They achieved low phase
variation at different gain states. However, the gain is
degraded by the phase-compensation circuit. Another widely
used topology is current-steering [4]. But the parallel
cascading stages in current-splitting VGA also exacerbates the
overall gain.
In this paper, a broadband VGLNA in 90-nm CMOS
technology for millimeter-wave phased-array systems is
presented. The gain control range is expanded by cascading a
PMOS gain-boosting current steering stage and a modified
current steering stage with the inductive phase inversion
network. The phase variation is reduced, also. The gm-
boosting and single-ended neutralization techniques are used
in the first and second stage, respectively； for the higher gain
and lower noise figure with relatively low power consumption.
Compared with similar previously reported works, the
proposed VGLNA exhibits high peak gain with low dc power,
and low RMS phase error within 9.8-dB gain control range.
II. CIRCUIT DESIGN
The circuit consists of four stages, as shown in Fig. 1. The
first two stages are two common source (CS) amplifiers in
cascade. A gm-boosting technique is utilized at the input stage
for simultaneous noise and input impedance matching [6]. In
addition, a drain-source transformer feedback neutralization is
used at the second stage to cancel the parasitic effect of the
transistor (M2) [9]. The two PMOS gain-boosting variable
gain stages in cascade with the inductive phase inversion
network are used for wideband low phase variation.
A. gm-Boosting Technique
In the conventional approaches, the source-degeneration
inductor and the gate series inductor are usually used in the
input stage for simultaneously noise and input impedance
matching. However, the loss of series inductor is normally
high, and contributes a lot to the noise figure. To solve this
problem, a gm-boosting technique is adopted for
simultaneously noise and impedance matching without the
M1 M2
M3
Vd
Vg1
RF input
RF
output
Vctrl
M4
M5
Vg2
M7
M6
M8
L1 = 332 pH L10 = 328 pH Device size:
L2 = 254 pH L11 = 80 pH M1,M2:2μm×20F
L3 = 230 pH L12 = 316 pH M3,M6,M4,M7:3μm×20F
L4 = 240 pH L13 = 190 pH M5,M8:2μm×30F
L5 = 150 pH C1 = 120 fF
L6 = 200 pH C2 = 136 fF
L7 = 120 pH C3 = 110 fF
L8 = 180 pH C4 = 126 fF
L9 = 342 pH C5 = 120 fF
Vg1 = 0.5V
Vg2 = 0.8V
Vd = 0.8V
Vd1 = 1V
Vg1 Vg1
Vd Vd1
Vg2
Vg1Vd1 Vctrl
Vd1
Vd1
C1
L1
L2
L3
C2
L5
L6
L7 L7
L8
L9
L10
C3
C4
L11
L12
L13
C5
K1 = 0.5
Lp1 = 350 pH
Ls1 = 180 pH
K2 = 0.55
Lp2 = 150 pH
Ls2 = 120 pH
L4
Phase Compensation
Network
Fig. 1. Schematic of proposed VGLNA.
978-1-6654-0307-8/21/$31.00 © 2021 IEEE 2021 IEEE/MTT-S International Microwave Symposium
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series inductor in this design [6]. The equivalent circuit of this
topology is shown in Fig. 2(a). Fig. 2(b) compares the noise
performances of the conventional L-C matched stage and gm-
boosting stage including the loss of all components. The
optimal noise impedance is close to the input impedance by
using the source-degeneration, and the series inductors at the
input signal path eliminated. The gm-boosting stage shows
better noise performance, as shown in Fig. 2(b).
B. Single-ended Neutralization Technique
The gate-drain parasitic capacitance (Cgd) of the transistor
generates a feedback path and degrades the gain and stability
at mmW frequencies. The single-ended neutralization
technique is adopted to reduce the impact of Cgd, and the
Miller effect can be reduced effectively. So the gain and
stability can be enhanced at high frequency [9]. As shown in
Fig. 3(a), this technique uses the transformer (TF) feedback
between drain and source inductors of a CS transistor. When
the feedback transformer is designed as:
gs
gd
n C
k C
≈ (1)
where n and k are the turn ratio and coupling coefficient of the
transformer, the Cgd can be cancelled. Fig. 3(b) shows the
comparison of MSG/MAG and stability factor with and
without transformer feedback, the stability and gain are both
improved. The uncertainty of the small-size neutralization
capacitor due to process variation can be avoided by the
neutralization method.
C. Wideband Phase Compensation Technique
To achieve broadband low phase-variation in different
gain states, the proposed current steering stage and modified
current steering stage with phase-inversion network are used
in the third and fourth stage. The proposed current-steering
stage is shown in Fig. 4(a). Fig. 4(b) exhibits the simulated
gain and phase variation of this circuit. As shown in Fig. 4(b),
when Vctrl is increased, the gain increasing, and the phase-
delay is reduced. Therefore, an inductive phase-inversion
network is added to the fourth of this VGA to reverse the
phase variation trend, as shown in Fig. 5(a). Fig. 5(b)
demonstrates the simulated gain and phase-variation of the
current-steering stage with a phase-inversion network. As
shown in Fig. 5(b), the trend of phase-delay versus Vctrl is
reversed after adding the phase-inversion network. The PMOS
current-steering method is adopted in this work. According to
[5], the output impedance of this circuit is independent to gm3.
Therefore, the linearity is improved. The source inductor Ls is
used for broaden the frequency range of phase compensation
in the current-steering stages with phase-inversion network.
Moreover, a smaller value of L1 can be selected, which makes
output return loss and the overall gain better than those in [3].
Fig. 6 compares of RMS phase error with and without Ls.
Thus, the two stages using phase-inversion network in this
work can properly compensate the phase variation in different
gain states in a wide frequency range.
III. EXPERIMENTAL RESULTS
The chip is fabricated in 90-nm CMOS and occupies a core
area of 0.45 mm2, as shown in Fig. 7. The circuit consumes a
Cpad
180。
Cgs gmVgs
i1
i2
iL1 iL2
Yin
k1i2
k2i1
20 25 30 35 40 45
2
3
4
5
g
m
-boosting stage
Conventional L-C Matching

N
o
is
e
F
ig
u
re
(
d
B
)
Frequency (GHz)
(a) (b)
Fig. 2. (a) Equivalent small signal model of gm-boosting stage. (b) Simulated
noise figure of the first stage using conventional L-C matching and gm-
boosting.
RFin
VDD
Vg1
RFout
20 25 30 35 40 45
2
6
10
14
18
22
MSG/MAG w/TF feedback
Stability Factor w/TF feedback
MSG/MAG w/o TF feedback
Stability Factor w/o TF feedback

M
S
G
/M
A
G
(
d
B
)
Frequency(GHz)
0
1
2
3
4
5
S
ta
b
il
it
y
F
a
c
to
r

(a) (b)
Fig. 3. (a) Schematic of the single-ended neutralization, (b) MSG/MAG and
stability factor with and without transformer feedback.
M1
M3
Vg2
Vg1
RFin
RFout
VDD
VCTRL
VDD
RF Choke
M2

0.4 0.6 0.8 1.0
2
3
4
5
6
7
8
Gain(dB)
Phase(deg)

G
a
in
(d
B
)
Vctrl(V)
121
122
123
124
125
126
127
128
P
h
a
se
(d
e
g
)

(a) (b)
Fig. 4. (a) Schematic of the proposed current-steering stage (b) Simulated gain
and phase variation.
M1
M3
Vg2
Vg1
RFin
RFout
VDD
VCTRL
VDD
M2
L1
L2
Bypass
Lm
Phase Inversion
Network
0.4 0.6 0.8 1.0
2
3
4
5
6
7
8
Gain(dB)
Phase(deg)

G
a
in
(d
B
)
Vctrl(V)
62
64
66
68
70
72
74
76
78
80
P
h
a
se
(d
e
g
)

(a) (b)
Fig. 5. (a) Schematic of the current-steering stage with inductive phase-
inversion network (b) Simulated gain and phase variation.
25 30 35 40 45
0
1
2
3
4
5
6
without L
s

with L
s

R
M
S
P
h
a
se
E
r
r
o
r
(
d
e
g
)
Frequency(GHz)
Fig. 6. Simulated RMS phase error with and without Ls.
765
dc power of 17.9 mW from the 1-V supply. The S-parameters
are measured from 10 MHz to 67 GHz using a Keysight
Microwave Network Analyzer PNA-X N5247A. Fig. 8(a)
shows the simulated and measured S-parameters from 23 GHz
to 45GHz at the highest gain state. The peak gain is 21.4 dB at
37 GHz, 3-dB bandwidth covers from 26 to 30.5 GHz and
33.8 to 40.6 GHz. The measured gain control function is
shown in Fig. 8(b). When control voltage decreases from 1 V
to 0.24 V, the gain drops from 21.4 to 11.6 dB at the peak gain
frequency. As shown in Fig. 9, the phase variation is less than
7.2° across the 3-dB bandwidth. Fig. 10(a) shows the RMS
phase error of the VGLNA. The RMS phase error is less than
4.32° in the 3-dB bandwidth. The simulated and measured
noise figures are exhibited in Fig. 10(b). The lowest noise
figure is 4.7 dB at 36 GHz. The measured large signal
performance at 28 and 38 GHz are shown in Fig. 11(a), (b),
respectively. The OP1dB are -4 and -4.7 dBm at 28 and 38
GHz, respectively.
Table 1 summarizes the performances of previously
reported VGAs. The proposed VGLNA exhibits the highest
FOM among all the previously reported low phase variation
CMOS VGAs.
IV. CONCLUSION
In this paper, a fully integrated broadband VGLNA in 90-
nm CMOS technology is presented. The gm-boosting
technique is adopted in the first stage to achieve low noise.
The single-ended neutralization technique is applied to
improve overall gain and stability. The phase variation is
reduced using two stages with phase compensation technique.
The VGLNA demonstrates high peak gain, low noise
performance, low phase variation and low RMS phase error
across the desired bands. This work is competitive among the
published CMOS VGLNAs and shows the potential for mmW
5G phase-array systems.
ACKNOWLEDGEMENT
The chip is fabricated by Taiwan Semiconductor
Manufacturing Company (TSMC), Hsinchu, Taiwan through
Taiwan Semiconductor Research Institute (TSRI) in Taiwan.

Fig. 7. Microphotograph of the proposed VGLNA.
20 30 40 50
-20
-10
0
10
20
S
21
(Meas.) S
21
(Sim.)
S
11
(Meas.) S
11
(Sim.)
S
22
(Meas.) S
22
(Sim.)


S
-P
a
ra
m
et
er
s
(d
B
)
Frequency (GHz)
20 25 30 35 40 45 50
-10
-5
0
5
10
15
20

G
a
in
(d
B
)
Frequency(GHz)
Vctrl(1V) Vctrl(0.6V) Vctrl(0.5V)
Vctrl(0.4V) Vctrl(0.3V) Vctrl(0.24V)

(a) (b)
Fig. 8. (a) Simulated and measured S-parameters. (b) Measured S-parameters
for various gain states.
23 25 27 29 31 33 35 37 39 41 43 45
-2
0
2
4
6
8
10
12
Vctrl(1V) Vctrl(0.6V) Vctrl(0.5V)
Vctrl(0.4V) Vctrl(0.3V) Vctrl(0.24V)

R
el
a
ti
v
e
P
h
a
se
S
h
if
t(
d
eg
)
Frequency(GHz)
Fig. 9. Measured relative phase shift at different gain states.
23 25 27 29 31 33 35 37 39 41 43 45
0
1
2
3
4
5

R
M
S
P
h
a
se
E
r
ro
r
(d
eg
)
Frequency(GHz)
26 28 30 32 34 36 38 40 42
4
5
6
7
8
9
10
11
Simulation
Measurement


N
o
is
e
F
ig
u
re
(d
B
)
Frequency(GHz)
(a) (b)
-30 -25 -20 -15 -10 -5
0
4
8
12
16
20
Gain(Meas)
P
out
(Meas)

G
a
in
(
d
B
)
P
in
(dBm)
-20
-15
-10
-5
0
P
o
u
t(
d
B
m
)
-30 -25 -20 -15 -10 -5
0
4
8
12
16
20
Gain(Meas)
P
out
(Meas)

G
a
in
(
d
B
)
P
in
(dBm)
-20
-15
-10
-5
0
P
o
u
t(
d
B
m
)

(a) (b)
Fig. 11. Measured power performance. (a) 28 GHz. (b) 38 GHz.
Table 1. Comparison of the state-of-the-art low phase variation CMOS VGAs.
Ref. Process
3-dB BW
(GHz)
Peak Gain
(dB)
Gain Control
Range(dB)
Phase Variation
(deg.)
RMS Phase Error
(deg.)
Pdc (mW) Noise Figure (dB)
FOM*
(1/mW)
[1] 65-nm 20~43 14.5 21.5 <2⁕ N/A 30.8 5.5 0.17
[2] 65-nm 27~42 9.6 7.5 <2.5 <3.5 15.6 N/A 0.19
[3] 65-nm 38~40 22 16 3.18@40GHz <2.67 38 6.3 0.33
[7] 65-nm 33.5~39 21 31 N/A <5.4 28 4 0.4
[8] 65-nm 30~34.5 20.8 10.6 <8 <3 26.7 3.71 0.41
This
work
90-nm
26~30.5
33.8~40.6
21.4 9.8
<3.4#
<7.2
<1.8#
<4.32
17.9 4.7 0.66
# 26~30.5GHz ⁕ < 37GHz *FOM = [S21,mag

/Pdc(mW)]
Fig. 10. (a) Measured RMS phase error. (b) Simulated and measured noise
figure when VGLNA is at the maximum gain state.
766
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