A33787 Any calculator
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Calculators may be used in this examination but must not be used to store text.
Calculators with the ability to store text should have their memories deleted prior
to the start of the examination.


Special Requirements: None










School of Engineering
Department of Electronic, Electrical and Systems
Engineering


Level H


04 30067


Electronic Engineering


Mock Examinations 2021


Time Allowed: 3 hours


Answer TWO questions from SECTION A,
and TWO questions from SECTION B


The allocation of marks within each question is stated in the right-hand
margin.



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SECTION A
(ANSWER TWO QUESTIONS)


1. (a) Three possible logic gate configurations are shown in Figure 1. For each
configuration, state whether or not they are legal CMOS configurations. If a
configuration is legal, then explain what its logic function is. If a configuration
is not legal, then explain why not and what the consequence of the error
would be.


Figure 1
















[5]




(b) Consider the following piece of VHDL code:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY q1b IS
END ENTITY q1b;

ARCHITECTURE dataflow OF q1b IS
SIGNAL a: STD_LOGIC:=’1’;
SIGNAL b, c: STD_LOGIC:=’1’;
SIGNAL d, e: STD_LOGIC;
BEGIN
c <= a NOR b AFTER 3 NS;
d <= NOT (a XOR c) AFTER 8 NS;
e <= NOT (a XOR c) AFTER 3 NS;
a <= '0', '1' AFTER 19 NS;
b <= '1', '0' AFTER 12 NS;
END ARCHITECTURE dataflow;

Sketch a waveform to show how the signals a, b, c, d and e change with
time.

Explain how your result is derived.

Explain the key features of the waveforms.






















[9]





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Question 1 continued...


(c) Consider the logic circuit shown in Figure 2.



Figure 2

The following four listings attempt to reproduce the functionality of the
circuit of Figure 2 by using a process. Explain briefly which of these listings
achieves the required functionality, and why (or why not). Unless otherwise
stated, you should assume that a, b, c, d and e are declared as signals.


(i)

PROCESS (a,b,c,d)
BEGIN
e <= c NOR d;
c <= a AND b;
d <= a OR b;
END PROCESS;



(ii) PROCESS (a,b)
VARIABLE c,d: STD_LOGIC;
BEGIN
e <= c NOR d;
c := a AND b;
d := a OR b;
END PROCESS;



(iii)

PROCESS (a,b)
BEGIN
e <= (a AND b) NOR (a OR b);
END PROCESS;



(iv)

PROCESS (a,b)
VARIABLE c,d: STD_LOGIC;
BEGIN
c := a AND b;
d := a OR b;
e <= c NOR d;
END PROCESS;







[6]






a
a
b
b
c
d
e
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2 (a) Explain briefly the factors that have led to the steady increase of
microprocessor clock frequency across the last few decades. Explain briefly
what factors limit the increase of clock frequency, and why increases of clock
frequency may not be matched by increases in performance.




[4]



(b) Figure 3(a) shows a datapath built up from five blocks of combinational logic.
The latency of each block is shown in the figure. Figures 3(b), 3(c) and 3(d)
show different possible ways to pipeline the datapath.


Figure 3


(i) Calculate the latency and throughput of the datapath in Figure 3(a). How
long would it take for the datapath to process 5000 data inputs?


[2]

(ii) For each of the pipelined versions, Figures 3(b), 3(c) and 3(d), calculate the
latency and throughput. Also calculate the time taken to process 5000 data
inputs. Comment briefly on the differences between the performance of the
three different pipelining schemes, and state which has the best
performance





[4]





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Question 2 continued...
(c) Figure 4 shows the core of a simple RISC microprocessor. The ALU uses
two pipeline stages, EX1 and EX2, in order to increase its clock frequency.
For this processor, the assembler code for simple arithmetic instructions
uses two source registers connected by an arithmetic operation and a
destination register. Here is an example:

r3  r1 - r2; subtract the contents of reg 2 from reg 1
and put result into reg 3

A jump instruction tests a condition on a register, and then jumps to another
statement if the condition is true. Here is an example:

if ( r1==0 ) jump to statement 4

When a jump instruction is processed, the jump instruction must have
reached the EX2 stage before it can be decided which instruction should be
read into the IF stage.


Figure 4

The following code fragment is to be executed on this processor

1: r1  r14 + r13;
2: r4  r18 + r16;
3: r7  r15 + r19;
4: r10  r11 + r7;
5: if (r20==0) jump to statement 8;
6: r6  r5;
7: r5  r1;
8: r2  r4;
9: r12  r6 + r5;
10: r8  r14;
11: r11  r13;
End of program;

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Question 2 continued...



(i) Identify locations in the above code where a data hazard and a control
hazard occur. Explain your reasoning.


[2]

(ii) Show how these hazards could be resolved by the compiler inserting no-ops
into the code, and quantify what impact this has on the throughput of the
microprocessor when running this code.



[3]

(iii) Show how these hazards could be resolved by the compiler using code
reorder and delayed branching to maximise the throughout. Calculate the
resulting throughput for the code.



[5]
























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3 (a) Explain briefly why testability is an important issue in the design of modern digital
systems. Explain how built-in-self test can be applied to an integrated circuit.


[4]

(b) Figure 5 shows a full adder circuit.

a

b

c

d

e

f

g


Figure 5

The circuit is to be tested using a test pattern generator based on the linear
feedback shift register (LFSR) shown in Figure 6.


Figure 6

Assume that the flip flops of the LFSR can be pre-set to a value of 1. Starting
from this condition, show the sequence of states the LFSR goes through.
Would this LFSR be a good choice as a test generator? Why or why not?




























[4]

(c) Now use a path sensitization method to produce a minimal set of test vectors
that can test the circuit of Figure 5 for single s-a-0 and s-a-1 faults on its
internal nodes. Explain the main differences between this approach to
testing, and the approach used in part (b).




[6]

(d) Write down the Boolean logic expression corresponding to the circuit Figure
5. Derive expressions for
(i) the Boolean difference of the output f with respect to the input a,
(ii) the Boolean difference of f with respect to b, and
(iii) the Boolean difference of f with respect to c

Explain the significance of your result.






[6]


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SECTION B
(ANSWER TWO QUESTIONS)

4.

Figure 1 shows a power amplifier using a pair of bipolar junction transistors
with the following specifications: TJmax = 150oC, θJA = 50oC/W, θJC = 4 oC/W
.





Figure 1
(a) What is the class of this amplifier? [1]

(b) Assuming a sinusoidal input signal, vin = Asin(ωt), derive expressions for:

(i) The average power dissipated by the load, RL. [2]

(ii) The average power drawn from the power supplies. [3]

(iii) The average power dissipated by the transistors. [1]

(iv) The efficiency of the amplifier. [1]

(c) What is the peak efficiency of the amplifier? [2]

(d) What is the maximum power dissipated by the transistors? [3]

(e) Calculate the minimum rating for any heatsinks required for safe
operation up to an ambient temperature, TA = 60oC.
[4]

(f) If the input signal is now a square wave with a peak amplitude of ± A,
derive an expression for the efficiency of the amplifier.
[3]

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5. Figure 2 shows a common-emitter amplifier using an NPN transistor with
a current gain, β, of 300, base-spreading resistance, rbb, of 40 Ω and
junction capacitances CBE and CBC of 10 pF and 6 pF, respectively. The
transistor in the circuit has a quiescent base-emitter voltage, VBE, of
0.5 V.




Figure 2

(a) Calculate the quiescent collector current needed to minimise the noise
figure of the amplifier.
[2]

(b) Assuming the noise figure is minimum, calculate RE and RC so that the
amplifier has a voltage gain of -120.
[5]

(c) Calculate the noise figure of the amplifier (neglect flicker noise). [5]

(d) Calculate the lower and upper cut-off frequencies of the amplifier. [3]

(e) What voltage gain would be required to increase the upper cut-off
frequency of the amplifier to 3 MHz?
[3]

(f) Are new values for RE and RC required for this amplifier to have an upper
cut-off frequency of 3 MHz while still having a minimum noise figure? If so,
calculate them where necessary.
[2]

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6. Figure 3 shows the circuit diagram of a 5th order Chebyshev low-pass filter
with a cut-off frequency of 60 kHz


(a) Sketch an equivalent circuit using only capacitors, resistors, and Frequency
Dependent Negative Resistors (FDNRs). Assuming that only 5 nF capacitors
are available, calculate the appropriately scaled component values.
[7]

(b) Sketch the circuit diagram of a grounded Generalised Impedance Convertor
(GIC) circuit.
[4]

(c) Calculate the component types and values required to simulate the FDNRs in
part (a) using the GIC circuit. Assume, again, that only 5 nF capacitors are
available.
[3]

(d) Sketch your completed active filter design. Include loss resistors, with the
appropriate values, for low-frequency stability in your design.
[6]


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A33787 Electronic Engineering






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