程序代写案例-ELE2018
时间:2022-04-02
ELE2018
Exam Time Table
Code ELE2018

Approved Calculators Permitted
Use Section A and Section B Answer Books
Linear Graph Paper

Faculty of Engineering and Physical Sciences
Examination for the Degree of Bachelor of Engineering -
Master of Engineering in Electrical and Electronic Engineering
and Software and Electronic Systems Engineering

Electronics 2

Tuesday, 14th May 2019 9:30 AM - 12:30 PM

Examiners: Prof X P Zhang
Dr S J N Mitchell, Dr N Buchanan
and the Internal Examiners



Write on both sides of the answer paper

Answer TWO questions from Section A and TWO questions from
Section B
All questions carry equal marks
You have THREE hours to complete this examination paper
Paper carries 70% of marks for the module
ELE2018


Table of constants



Electronic charge q 1.6 × 10-19 C

Boltzmann’s constant k 1.38 × 10-23 J K-1
or 8.62 × 10-5 eV K-1

Room temperature T 300K

q
kT
at Room Temperature (300K) V0259.0=
q
kT

Permittivity of free space εo 8.85 × 10
-14 F cm-1

SILICON (at 300K)
density 2.33 g cm-3
atomic weight 28 g mol-1
atoms/cm3 5 × 1022 cm-3
relative permittivity εSi 11.7
intrinsic carrier concentration ni 1.45 × 10
10 cm-3
bandgap Eg 1.12 eV
electron affinity Χ 4.05 eV


SILICON DIOXIDE (at 300K)
density 2.2 g cm-3
molecular weight 60 g mol-1
molecules/cm3 2.2 × 1022 cm-3
relative permittivity εox 3.9
Page 2 of 10
ELE2018

Standard Equations

Basic:
dx
dE
q
1
=E pp
q
kT
D µ= ppp DL τ=
kT
q
i
Fp
enp
φ
=0 FpiFp EEq −=φ
kT
q
i
Fn
enn
φ
=0 iFnFn EEq −=φ
Drift: EpqJ pp µ= EnqJ nn µ=
Diffusion:
dx
dp
qDJ pp −=
dx
dn
qDJ nn=
Diodes: FnFpV φφ +=0 






=
20
ln
i
DA
n
NN
q
kT
V
−+ === QxqNxqNQ pAnD

AD
ADD0Si
NqN
NNV
W
)(2 +
=
εε







=
kT
qV
pp Anon exp)0( 
















−





=−
p
A
n0n0n
L
x
Tk
Vq
ppxp exp1exp)(






−





= 1exp
kT
qV
II aSD








+=
An
n
Dp
p
iS
NL
D
NL
D
AqnI 2

g
i
GEN
WAqn
I
τ
=
6
1
1






=
BD
R
V
V
M
Page 3 of 10
ELE2018

Bipolar transistor: (equations for p-n-p device)






=
kT
Vq
NW
nDqA
I EB
DBB
ipBE
DB exp
2






=
kT
Vq
NW
nDqA
I EB
AEE
inEE
DE exp
2

DB
pB
B
RB I
L
W
I
2
2
2
= 





=
kT
qV
II EBR0R
2
exp

I+I+I
I
=
DERDB
DBγ
I+I+I
I-I
=
DERRB
RBDBβ

MOS transistor: F
ox
dep
ox
F
msT
C
Q
C
Q
V φφ 2±−−=
S0Sidep qNQ φεε2±=
( )[ ]221 DSDSTGSOXnDS VVVVLCWI −−= µ
Oxidation: ( ) τ−+= OO XAX
B
t 2
1
( )ii XAX
B
+= 2
1
τ
Diffusion:
pi
Dt
CQ ST 2=
After drive-in 






=
Dt
x
CC otx
4
exp
2
),(
Dt
Q
C To
pi
=
Ion Implantation:
( )









−−
= 2
2
)(
2
exp
P
P
Px
R
Rx
CC pi2PPT RCQ ∆=
Page 4 of 10
ELE2018

Section A


Q1. (a) A silicon pn junction has an acceptor concentration of 5 × 1016 cm-3 on
one side of the junction and a donor concentration of 1 × 1015 cm-3 on the
other side. Calculate the built-in voltage and the total depletion region
width at a reverse bias of 10 V. [10 Marks]

A two-stage boron diffusion process should be designed to produce a
surface concentration of 5 × 1018 cm-3 and a junction depth of 1.1 µm in an
n-type silicon substrate which had a uniform dopant concentration of
1 × 1015 cm-3. The first stage is a solid solubility limited, boron diffusion
at 900oC. This is followed by a drive-in at 1050oC.
Solid Solubility Limit for boron at 900oC = 1.0 × 1020cm-3
Diffusivity of boron at 900oC = 1.5 × 10-15 cm2s-1
Diffusivity of boron at 1050oC = 9.0 × 10-14 cm2s-1
(b) Calculate the total drive-in D2t2 product and hence the time t2
required for the drive-in step. [7 Marks]
(c) Calculate the dose of boron to be introduced and the time t1 required
for the first stage of the process. [8 Marks]

Page 5 of 10
ELE2018

Q2. (a) With the aid of cross-section diagrams outline a process sequence for
the fabrication of an n-channel polysilicon gate MOS transistor. [7 Marks]
(b) The n-channel MOS transistor should be designed to have a threshold
voltage of 1.0 V. If the doping concentration in the silicon substrate is
5 × 1015 cm-3, calculate the required thickness of the gate oxide. The gate
electrode is n+ polysilicon and you may assume that there is no fixed
charge in the oxide. [12 Marks]
(c) The gate oxide thickness calculated in part (b) is to be grown on a bare
silicon surface, using a dry oxidation process at 1050°C. Given the
oxidation parameters below, calculate the time required for the oxidation
process.
A = 0.18 µm, B = 0.016 µm2/hr [6 Marks]

Page 6 of 10
ELE2018

Q3. (a) A pn junction is to be formed by ion implantation of phosphorus into
a silicon wafer that has a uniform boron concentration of 1 × 1015 cm-3.
The n-type layer is required to have a peak concentration of 1 × 1019 cm-3
at the silicon surface and the pn junction should be 0.2 µm below the
silicon surface.
Design the ion implantation process by calculating the following
parameters.
(i) the implantation energy.
(ii) the implantation dose.
(iii) the thickness of silicon dioxide to be used.
[6 marks]
[4 marks]
[3 marks]
(b) After the implantation in part (a), the silicon wafer was subjected to a
1 hour anneal at 1000 °C in nitrogen. Calculate the peak phosphorus
concentration and the junction depth after this anneal.
Diffusion coefficient of phosphorus at 1000°C = 2.6 × 10-14 cm2s-1. [12 Marks]











END OF SECTION A
Page 7 of 10
ELE2018

Section B
Q4. (a) List the advantages & disadvantages of an active filter in comparison to
a passive filter circuit.
(b) State the rate of fall-off in dB/decade of a 1st order, 2nd order and 3rd
order active filter.
[3 marks]
[3 marks]
(c) A first order low-pass filter is shown in Figure Q4. Show that its
transfer function is given by:
( )21
2
1
1
RCjR
R
v
v
1I
O
ω+

= .
[7 marks]
(d) If R1 = 10 kΩ then find C1 and R2 so that the gain of the low-pass filter
at low frequencies is 20 dB and the cut-off frequency is 8 kHz. [7 marks]
(e) Sketch a Bode plot for the magnitude of the transfer function for the
above filter, clearly marking the axes. [5 marks]


Figure Q4


Page 8 of 10
ELE2018

Q5. An amplifier circuit using a bipolar transistor is shown in Figure Q5.
(a) State, with a valid reason, whether this amplifier is an emitter follower
or a common emitter configuration. [3 marks]
(b) Redraw Figure Q5 as a large signal equivalent circuit. Show that:
( )60.v
R

- Vv I
B
CF
CCCE −=
[8 marks]
(c) Show that the input voltage, vISAT to produce the onset of saturation for
T1 is given by:
[ ] 6.0+−=
CF
B
CESATCCI R
RVVv
SAT β [6 marks]
In the circuit of Figure Q5, RC is now replaced by a lamp with a resistance
of 250 Ω. At least 55 mA is required to light the lamp. The circuit is to be
designed that the lamp is on for vI = 1 V. T1 has β = 100, VCESAT = 0.1 V,
Vcc = 15 V, RB = 650 Ω.

(d) For vI = 1 V, confirm, by calculation, that T1 is in saturation. [4 marks]
(e) Calculate the current in the lamp when T1 is in saturation and confirm
the current is sufficient to light the lamp.
[4 marks]

Figure Q5
Page 9 of 10
ELE2018

Q6. A common-source FET amplifier is shown in Figure Q6.

(a) Using appropriate models, show that the voltage gain at mid-range
frequency is given by: 





+
−=

DLds
DLds
mmidv
Rr
Rr
gA where LDDL RRR = .
[8 marks]
(b) Using appropriate models, show that the voltage gain at high frequency
is given by: 






T2O
midvv
CRj
AA
ω+1
1
=
where dsLDO rRRR = and gd
o
gs
dsT2 C
v
v
CC 





−+= 1 .
[9 marks]
(c) Given the transistor parameters and component values below,
determine the value of mid-frequency voltage gain, and the cut-off
frequency of the amplifier. [8 marks]

VDD = 15 V, R1 = 250 kΩ, R2 = 100 kΩ, RD = 10 kΩ, RL = 10 kΩ,
RS = 1 kΩ, CI = CO = CS = 10 µF,
FET1: gm = 2 mS, rds = 200 kΩ, Cgd = Cgs = 6 pF, Cds = 1 pF

CS
RS
RD
CO
CI
R2
vo
vi
R1
VDD
GND
RL
FET1


Figure Q6.


END OF EXAMINATION
Page 10 of 10


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