CSSE2010/7201 - Introduction to Computer Systems
Assignment 1: Digital Logic Design
Semester 1, 2022
Due: Thursday 14, April 4:00 pm (AEST)
This assignment is worth 20% of your grade. Revision 1.2.
This assignment involves the design and simulation of a digital circuit for the problem specified below. This
will consist of three tasks:
• Design Task: Design a circuit for the problem specification given below.
• Simulation Task: Simulate the circuit you designed in Logisim (or Logisim Evolution).
• Questions: Provide answers to a few questions about your design.
You are required to submit a single zip file containing the completed steps of the design task outlined below
and answers to the questions in a .PDF file (may be either handwritten and scanned or typeset) along with a
Logisim or Logisim Evolution file. See the Submission Process section below for more details.
Problem Description
Your task is to design a two-input digital lock system that unlocks only when the password 10010 is entered via
a given combination of two inputs. Here, 1 is the first bit and 0 is the last bit of the password. For the lock to
open, each bit in the password must appear on the correct input X or Y, with the exact input order depending
on the last digit of your student number as shown in table 1. The system has additional inputs to load digits
from the two inputs X and Y and to reset the sequence, and outputs whether the system is currently locked or
unlocked as well as the number of digits of the password that have been detected on the X input. The behaviour
of these inputs and outputs is further explained in table 2 and a diagram of the system is shown in figure 1.
Examples of the behaviour of the system are shown in figures 2 to 4 and table 3.
Last digit of 8-digit
student number
Input order to consider
for password detection
0-1 XYXXY
2-3 YYYXX
4-5 YXXYX
6-7 XXYXY
8-9 YXXXY
Table 1: Ordering of inputs required for the password to be detected.
Two-input
digital lock
Reset Button (1-bit)
Entry Button (1-bit)
Digit Y (1-bit)
Digit X (1-bit)
Unlocked (1-bit)
X digits detected (2-bits)
Figure 1: Block diagram of the two-input digital lock inputs and outputs.
1
Input/Output name Logisim Component Function
X Logisim Pin Selects either ‘0’ or ‘1’ for the X input
Y Logisim Pin Selects either ‘0’ or ‘1’ for the Y input
Entry Logisim Button Enters the selected digits on the X and Y inputs
Reset Logisim Button Clears all digits entered asynchronously
Unlocked Logisim LED Outputs ‘1’ when the system is unlocked, otherwise ‘0’
X digits detected Logisim LEDs
Outputs the number of digits of the password
currently detected on the X input
Table 2: Inputs and outputs of the two-input digital lock.
The following rules apply for the system:
• The system starts with empty sequences of digits i.e. with no digits entered.
• Only the digit on the correct next input is counted towards detection of the password e.g. if the next
element of the sequence is X then only the value of the X input is entered into the lock and the value of
the Y input is ignored.
• Digits are entered when the Entry button is pressed (i.e. transitions from ‘0’ to ‘1’ thus providing a rising
clock edge).
• The system must display whether it is currently locked (‘0’) or unlocked (‘1’) to a Logisim LED labelled
Unlocked.
• The system must display the number of digits currently detected towards the X elements of the password
using two Logisim LEDs labelled L1 (the MSB) and L0 (the LSB). This number starts at ‘0’ and is
incremented every time a correct digit is successfully entered on the X input. This value is reset if a new
detection of the password begins.
• If the Reset button is pressed at any time, all digits entered are immediately cleared. This is an asyn-
chronous reset, occurring immediately when the Reset button is pressed, separate to the main clock
provided by the Entry button. The lock should not operate while the Reset button is held down.
• The system detects whether the password has been entered at the end of the sequence of digits entered.
The system will still unlock if incorrect digits are entered prior to the correct password being entered and
detected. This behaviour is shown in figure 2 and table 3.
• The system becomes locked again as soon as any other digit is entered when the system is unlocked or
the Reset button is pressed.
• The system does not detect ‘overlapping’ of passwords. Once the system has been unlocked a subsequent
unlock can only occur by correctly entering all digits of the password on the correct inputs again. This
can occur directly from the unlocked state i.e. the first digit of the password can be detected as soon as
the system has been unlocked. See the example in figure 3 for the expected behaviour.
Examples
A collection of examples detailing the behaviour of the two-input digital lock are shown below in figures 2 to 4
and table 3. For each of the examples
• The password is 10010. The digits of the password are detected left-to-right i.e. the first digit to match
is 1. On the diagrams, digits are entered according to the CLK index (from the inside to the outside).
• For the examples,the password input order is XYXYX.
• The outlined digit indicates whether X or Y is the current input being detected.
• The coloured boxes correspond to the password digits being successfully detected.
• The output behaviour corresponds to after the inputs have been entered (i.e. after the Entry button has
been pressed).
2
Two-input
digital lock
Reset
Entry
Y
X
Unlocked
X digits
entered
CLK index
0
1
1
0
00
1
1
1
2
0
01
2
0
0
3
0
01
3
0
1
4
0
10
4
0
1
5
0
10
5
0
1
6
1
11
6
0
0
7
0
00
7
Figure 2: Example of the correct password being entered and detected. The same example is shown in tabular
form in table 3.
Two-input
digital lock
Reset
Entry
Y
X
Unlocked
X digits
entered
CLK index
1
1
1
0
01
1
0
0
2
0
01
2
0
0
3
0
10
3
0
1
4
0
10
4
0
1
5
1
11
5
1
1
6
0
01
6
1
0
7
0
01
7
0
1
8
0
10
8
0
1
9
0
10
9
0
1
10
1
11
10
Figure 3: Example of two successive detections of the password. As mentioned above, the system does not
consider overlapping.
Two-input
digital lock
Reset
Entry
Y
X
Unlocked
X digits
entered
CLK index
0
1
1
0
00
1
1
1
2
0
01
2
0
0
3
0
01
3
1
1
4
0
01
4
0
1
5
0
00
5
0
1
6
0
00
6
0
1
7
0
00
7
Figure 4: Example of the password not being detected. Note at CLK index 4, the previous detection fails but
a new detection starts. That new detection also fails.
Clock
index
Current inputs
(XY)
Digits
entered
Unlocked
status
Number of X
digits entered
1 01 0 0 00
2 11 0 1 0 01
3 00 0 10 0 01
4 01 0 100 0 10
5 01 0 1001 0 10
6 01 0 10010 1 11
7 00 0 10010 0 0 00
Table 3: Example of the correct password being entered and detected. This example matches the behaviour in
figure 2.
3
Design Task
Your task is to design a digital logic circuit to implement the two-input digital lock described above. You should
explicitly state any assumptions you make outside of the above specifications. As part of the design task you
will need to complete the following design steps:
1. Draw a state diagram for the two-input digital lock described above (hint: you should not require more
than 3 flip-flops to build this circuit with a basic encoding). Your state diagram should be complete and
drawn according to the standard guidelines mentioned in the lectures and labs. You do not need to include
the asynchronous reset input in the state diagram. (Hint: At each state only the current digit of interest
needs to be considered).
2. Create a two-dimensional/2D state table for your state diagram.
3. Choose two possible encodings for the states you have chosen (i.e. binary, Gray code or a custom encoding).
Do not use one-hot encoding for this task as this will lead to an overly complicated design.
4. Create two state tables (either 1D or 2D) corresponding to each of your two chosen encodings. Note
the 1D state table will have more rows (essentially a truth table) and the 2D state table will be more
compact and is recommended. You can determine the logic expressions (the next step) from either 1D or
2D state tables. Your state tables must consider any unused/‘don’t care’ states which must transition to
the initial/reset state when the Entry button is pressed i.e. the ‘next state’ of the ‘don’t care’ states must
be the initial/reset state.
5. Determine boolean expressions for the next state logic and output logic for both chosen encodings. You
are not required to simplify these expressions but it will make the next steps easier. Working is not
required however is strongly recommended as part marks may be awarded where only a minor error has
been made. You may determine logic expressions using inspection and you should state this if you have
done so.
6. Choose one encoding scheme to continue with. You will be asked to justify this decision in Question 1
below.
7. Draw a logic diagram for the two-input digital lock circuit given the chosen encoding. You may use gates
with more than 2 inputs. You should implement your logic expressions directly using logic gates only (do
not use combinational logic circuits such as adders, multiplexers etc.). Your logic diagram cannot be a
screenshot of the Logisim design, as this step in the design process occurs before you attempt to simulate
your design. You can either hand-draw the logic diagram or use a tool such as draw.io, Microsoft Visio
(available on UQ computers) or similar.
Simulation Task
As part of the design task you should have drawn a logic diagram for the two-input digital lock circuit. The
simulation task is to construct this circuit using Logisim (or Logisim Evolution). This Logisim (or Logisim
Evolution) file should be submitted in your zip file and named as per the Submission Process section that
follows.
Questions
As part of your submission you should include written answers to the following questions:
Q1: In step 6 of the design task, you chose one of two encodings to use for the circuit constructed in Logisim,
why did you choose that encoding? Justify your decision by providing the complexity for each coding.
Here the complexity refers to the number of flip flops and AND, NAND, OR, NOR, XOR and XNOR logic
gates used. You should ignore any NOT gates in your analysis. You do not need to consider the number of
inputs of each gate (i.e. if you have two 2-input AND gates and a 3-input AND gate, count the total number
of AND gates as 3). (2 marks)
Q2: How did you test your Logisim circuit to ensure it worked correctly? You may include screenshots if it
helps your explanation but they are not necessary. (1 mark)
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Submission Process
Your submission should include a zipped folder (a .zip file only, not any other format such as .rar) containing
two files - a .PDF file and a Logisim (or Logisim Evolution) .circ file:
• Working for each of the 7 design steps and answers to each of the questions should be included in a .PDF
file called sXXXXXXX-a1.PDF where XXXXXXX is replaced by your seven (7) digit student username. The
document may be handwritten or typeset, if it is handwritten, please ensure it is neat and legible.
• Your Logisim (or Logisim Evolution) file should be included as a .circ file called sXXXXXXX-logisim.circ
if you used Logisim or sXXXXXXX-evolution.circ if you used Logisim Evolution. No other simulation
tools will be accepted.
This zip file must be named sXXXXXXX-a1.zip and should be submitted electronically to Blackboard according
to the exact instructions listed on the Blackboard website.
You can submit your assignment multiple times before the assignment deadline but only the last submission will
be marked. Only submit the zip file described above. You are responsible for ensuring that you have submitted
the files that you intended to submit, you are encouraged to download your submission from Blackboard and
ensure it contains the correct files.
Submitted work should be neat, legible and simple to understand - you may be penalised for work that is untidy
or difficult to read.
While you can collaborate to clarify any doubts in the learning material required for the assignment, the
work you submit must be your own and this is an individual assignment. If any signs of plagiarism/collusion
is detected or there are any doubts about the origin of your submission you may be requested to attend a
subsequent oral assessment as decided by the course coordinator. Failure to attend such an oral assessment or
failure to satisfactorily answer questions about your submission will result in zero marks for the assignment.
Late Penalties: Where an assessment item is submitted after the deadline, without an approved extension, a
late penalty will apply. The late penalty shall be 10% of the maximum possible mark for the assessment item
will be deducted per calendar day (or part thereof), up to a maximum of seven (7) days. After seven days, no
marks will be awarded for the item. A day is considered to be a 24 hour block from the assessment item due
time. Negative marks will not be awarded.
Criteria
This assignment will be marked out of 20 and is worth 20% of your overall grade.
State Diagram - 4 marks
4: Fully correct state diagram.
3: Mostly correct state diagram with at most one error.
2: Somewhat correct state diagram with more than one error.
1: Mostly incorrect state diagram with many errors.
0: Incorrect state diagram.
State Tables - 2 marks
Marked relative to the given state diagram. Your state tables must include unused states.
2: Fully correct state tables.
1: Mostly correct state tables, with only a few mistakes or missing unused states. Or only one state table
for one encoding.
0: No state tables or incorrect state tables.
5
Boolean Expressions - 3 marks
Marked relative to the given state tables.
3: Correct boolean expressions for all next state and output logic.
2: Mostly correct expressions with only a few minor errors.
1: Somewhat correct expressions with lots of minor errors or a major error/omission.
0: Work with little academic merit.
Logic Diagram - 3 marks
Marked relative to the chosen boolean expressions. Logisim screenshots are not accepted as logic diagrams.
3: Fully correct logic diagram.
2: Mostly correct logic diagram, with a few errors or omissions.
1: Somewhat correct logic diagram, with a lot of errors or omissions.
0: Missing logic diagram or a diagram containing major errors.
Logisim Simulation - 5 marks
Circuit functionality marked relative to the original problem definition.
5: Fully correct Logisim build, uses all specified components and functions correctly according to the problem
description.
4: Logisim build that is either fully correct for given state diagram or functions correctly with a minor error.
3: Logisim build that contains a few minor errors resulting in it not achieving the specified circuit function-
ality.
2: Logisim build with many errors that does not achieve the specified circuit functionality.
1: Logisim build that does not reflect the problem description.
0: Work with little academic merit.
Questions - 3 marks
Question 1
2: Answer to question 1 correctly analyses the chosen encodings and justifies the choice of chosen encoding.
1: Answer to question 1 partially analyses the chosen encodings and justifies the chosen encoding or contains
minor errors.
0: Answer to question 1 does not justify the chosen encoding according to the question requirements.
Question 2
1: Answer to question 2 provides a reasonable method of testing the circuit behaviour.
0: Answer to question 2 does not provide a reasonable method of testing the circuit behaviour.
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