程序代写案例-ELE2025
时间:2022-04-16
ELE2025
Exam Time Table
Code ELE2025

Approved Calculators Permitted
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Faculty of Engineering and Physical Sciences
Examination for the Degrees of Bachelor of Engineering
- Master of Engineering in Electrical and Electronic Engineering
and Software and Electronic Systems Engineering

Embedded Systems 2

Wednesday, 29th April 2020 9:45 AM - 9:45 AM

Examiners: Prof X P Zhang
Dr K McLaughlin, Dr M Cregan
and the Internal Examiners



Write on both sides of the answer paper

Answer any THREE questions
All questions carry equal marks
You have TWO hours to complete this examination paper
Paper carries 40% of marks for the module




Embedded Systems ELE2025


Q1. (a) Prove that + ̅. = + [5 Marks]

Questions 1(b), 1(c) and 1(d) refer to the function f, which can be
implemented as the circuit shown in Figure Q1.

Figure Q1

(b) Prove that f is equivalent to AB + AD. [5 Marks]

(c) Prove whether it is possible to implement f using only two 2-input
NOR gates. Assume inverted inputs, such as ̅, are available without
additional cost. Sketch a circuit to support your answer. [5 Marks]

(d) Prove whether it is possible to implement f using only three 2-input
NAND gates. Assume inverted inputs, such as ̅, are available without
additional cost. Sketch a circuit to support your answer. [5 Marks]

Question 1(e) is about the function g, where:
g = A ̅B̅ + C̅
(e) Implement g using only two logic gates. The gates can be any
standard type. You can use two of the same type of gate, or two different
types of gate. However, only A, B and C are available as inputs, so any
cost to invert must be included in your design. Sketch a circuit to support
your answer. [7 Marks]

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Embedded Systems ELE2025


Q2. (a) The circuit shown in Figure Q2 comprises combinational logic and a
number of edge-triggered data flip-flops. The circuit is designed to
advance through states, where the combination logic determines the
sequence of states. The process of advancing from one state to the next is
controlled by the clock signal, “Clk”.

Figure Q2

For the circuit, determine all possible states and the sequence of the
states. Sketch an appropriate state diagram, or diagrams, to describe the
operation of the circuit. [20 Marks]

(b) Sketch a timing diagram, or diagrams, showing the operation of the
circuit as it advances through all possible states. Your timing diagram
should show one signal for the clock and one output signal from each
flip-flop. Your diagram does not need to show propagation delays. [7 Marks]


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Embedded Systems ELE2025


Q3. (a) Using the Quine-McCluskey method, derive a minimal sum-of-
products solution for the function f(A,B,C,D,E).

f(A,B,C,D,E) = ∑ (2, 6, 13, 27, 29) + d(3, 4, 5, 14, 21, 26, 28, 31)

In your answer, clearly identify all Prime Implicants and Essential Prime
Implicants, and explain your reasons for selecting any Prime Implicants
as part of your solution. Note that inverted inputs are not available and
will therefore cost additional logic to implement. [20 Marks]



Figure Q3

(b) Sketch and clearly label a diagram representing the entity described
by the VHDL code shown in Figure Q3. [3 Marks]

(c) Explain, with a brief justification, what function is being implemented
by the VHDL code shown in Figure Q3. [4 Marks]


library IEEE;
use IEEE.std_logic_1164.all;

entity exam_entity is
port (a, b, c, d: in std_logic;
e: in std_logic_vector(1 downto 0);
f: out std_logic);
end exam_entity;

architecture exam_arch of exam_entity is
begin
process(a,b,c,d,e)
begin
case e is
when "00" => f <= a ;
when "01" => f <= b ;
when "10" => f <= c ;
when others => f <= d ;
end case;
end process;
end exam_arch;
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Embedded Systems ELE2025


Q4. (a) Develop a single finite state machine (FSM) circuit that can detect
sequences of two or more 0s, or two or more 1s, in a bit-serial data
stream.

Table Q4 gives an example of how the circuit should behave when it
receives the input sequence 1 0 1 1 1 0 1 1 0 0 1 0, where the input data
stream is labelled “x” and the output is labelled “z”

x 1 0 1 1 1 0 1 1 0 0 1 0
z 0 0 0 1 1 0 0 1 0 1 0 0

Table Q4

For example, the circuit output z will equal 1 when any of the sequences
00, 000, 0000, 11, 111, 1111, etc. are received as an input.

Use edge-triggered, preset/preclear, data flip-flops in your design, and
use minimal sum-of-products logic.

Start by sketching a graphical representation of the required FSM.

Before you derive the combinational logic, test your graphical FSM
design for errors by copying the input serial stream in Table Q4 and
check it against your design. [20 Marks]

(b) Sketch and annotate a diagram of the circuit that you developed in
part (a). [7 Marks]



END OF EXAMINATION
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