C代写-CSSE2010
时间:2022-05-31
Semester One Final Examinations, 2021 CSSE2010 Introduction to Computer Systems
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This exam paper must not be removed from the venue

Venue ____________________
Seat Number __________
Student Number |__|__|__|__|__|__|__|__|
Family Name ____________________
First Name ____________________


School of Information Technology and Electrical Engineering
EXAMINATION
Semester One Final Examinations, 2021
CSSE2010/7201 Introduction to Computer Systems
This paper is for St Lucia Campus students (All flexible delivery students and external mode students
who have been approved for an on-campus exam)

Examination Duration: 120 minutes

Reading Time: 10 minutes

Exam Conditions:

This is an Open Book examination
Casio FX82 series or a calculator on the UQ approved list
During reading time - write only on the rough paper provided
This examination paper will be released to the Library

Materials Permitted In The Exam Venue:
(No electronic aids are permitted e.g. laptops, phones, e-readers)

Calculators - Casio FX82 series or UQ approved (labelled)
Written or printed material is allowed

Materials To Be Supplied To Students:

None

Instructions To Students:

Additional exam materials (e.g. answer booklets, rough paper) will
be provided upon request.

Answer all questions on this exam paper.
Questions are worth the number of marks indicated



For Examiner Use Only

TOTAL:

Question

Mark

1



2



3



4



5



6



7



8



9




Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
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Question 1. (10 marks)
(a) Consider the octal number 1556. Write down the hexadecimal representation of this
number (1 mark)









(b) Consider the decimal number –98. Write down this number using each of the following
binary representations. (1 mark each)
i) 9-bit ones’ complement








ii) 8-bit two’s complement








iii) 10-bit excess-512








iv) 9-bit signed magnitude


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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 3 of 22
Question 1. (continued)
(c) What is the decimal value of the IEEE single-precision floating point number
0xB3A5C600. Show your working. (3 marks)




























(d) Consider the 10-bit two’s complement binary numbers 1110111010 and 1101101111.
i) What is the result (in 10-bit binary) of adding these two numbers? (1 mark)









ii) What would be the values (0 or 1) of the V (overflow), C (carry), N(negative)
and Z (zero) flags after the addition operation in (d)-(i) above? (1 mark)

V: C: N: Z:

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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 4 of 22
Question 2. (12 marks)
(a) Consider the logic function = . &&&&&. (⨁&&&&&&&)
i) Draw a logic circuit which implements this function only using 2-input AND, OR
gates and NOT gates. (2 marks)















ii) Complete the following truth table for Z. (2 marks)

A B C Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

iii) Write down a sum-of-products expression for Z. (2 marks)

Z =













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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 5 of 22
Question 2. (continued)
(b) Consider the logic function = . + '.
i) Draw a circuit which implements X from inputs A, B and C using only two-input
NAND gates. (2 marks)
















ii) Using a logic diagram, show how you can implement the above function X given in
(b)-i) using a 4 to 1 multiplexer. You do not need to show the gate level details of the
multiplexer (i.e. you can use the standard symbol for a 4 to 1 MUX). (4 marks)


















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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 6 of 22
Question 3. (10 marks)
(a) Using positive edge triggered D-flip flops and other gates, draw the logic diagram for a 3-
bit synchronous counter which counts through the sequence 000 à 001 à 100 à 011 à
110 à 101 à 111 à 010 à 000 à …
Show all your working. (5 marks)

























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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 7 of 22
Question 3. (continued)
(b) You are given a 4-bit adder/subtractor module having the 4-bit inputs A=A3A2A1A0 and
B=B3B2B1B0 and control input M (M=0 for addition and M=1 for subtraction), and the 4-
bit output S=S3S2S1S0 and carry out from the most significant bit C4. Show in a logic
diagram, how you can use this module to design a 4-bit signed comparator circuit to
detect whether A is greater than B in signed two’s complement format. That is, the final
output of the circuit F=1 if A > B (in signed two’s complement format) and F=0
otherwise. You can use basic logic gates freely and you do not have access to internal
signals of the 4-bit adder/subtractor module, such as the internal carry-in/out signals
(except for C4, which is the carry out from the MSB). (5 marks)






























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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 8 of 22
Question 4. (13 marks)
Consider the ALU bit slice shown below. [Note that for the output multiplexer on the right
hand side, F2 is the most significant of the select bits, so for example, if F2,F1,F0 =0,0,1 then
input 1 of the multiplexer will be selected.]


(a) Consider 16 of these ALU bit slices put together to form an 16-bit ALU (i.e. with 16-bit
data inputs A and B). Complete the following table to show the required control inputs for
the ALU to perform the given functions. (Each control input will have value 0 or 1 or X
(don’t care). The “carry in” control input applies only to the least significant bit, the
“carry in” input of other bit slices comes from the “carry out” output of its neighbouring
bit slice. The “right shift in” control input applies only to the most significant bit; the
“right shift in” input of other bit slices comes from the “right shift out” output of its
neighbouring bit slice.) If it is not possible to generate the given function, make a
comment to this effect below the table. If there is more than one way to generate the
given function, just show one way.
(2 marks each)
Description of
Function Output ENA INVA ENB INVB
Carry
In
Right
Shift
In F2 F1 F0
(i) Increment A (i.e., A+1)
(ii) Decrement B (i.e., B-1)
(iii) Logical shift left of B
(iv) * + ' (bitwise)(+ is OR)

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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 9 of 22
Question 4. (continued)
(b) Write AVR assembly code segments to carry out the following operations. You may use
registers other than specified freely as you wish.

i) Initialise a 16-bit signed variable (in two’s complement) stored in registers r8:r9 to
value (-2). r8 contains the most significant byte and r9 contains the least significant
byte. (1 mark)









ii) Multiply an 8-bit signed variable (in two’s complement) stored in r5 by 7 and place
the result in r6, without using any variant of the multiplication instructions and only
using shift/rotate/addition/subtraction operations. You must use only 6 instructions or
fewer to accomplish this task. (2 marks)












iii) Divide a 16-bit signed variable (in two’s complement) stored in r9:r10 by 4 and place
the result back in r9:r10, if r9 stores the most significant byte and r10 stores the least
significant byte. (2 marks)
















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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 10 of 22
Question 5. (11 marks)
This question applies to the AVR ATmega324A microcontroller.
(a) Write down the machine code corresponding to the AVR assembly language instruction
mov r18, r21 (1 mark)




(b) What will be the binary value in register r30 after the execution of the nominated
instructions (i) to (x) in the sequence of instructions below. Note that the instructions are
not independent – registers and RAM maintain their values from one instruction to the
next. You may assume that the stack pointer has been appropriately initialised. (1 mark
each)
ldi r30, 0x17
push r30
ldi r30, 0166 (i) r30:
dec r30 (ii) r30:
ldi r30, $FE (iii) r30:
ldi r17, 100
lsl r17
rol r30 (iv) r30:
ldi r30, 0x50
clr r31
st Y+, r30 (v) r30:
ldi r30, low(595) (vi) r30:
ldi r31, high(595)
adiw ZH:ZL, 8 (vii) r30:
ser r30 (viii) r30:
push r30
inc r30
pop r30 (ix) r30:
pop r30 (x) r30:

Q5

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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 11 of 22
Question 6. (13 marks)
For each of the following C statements for the Atmel AVR ATmega324A, write down the
assembly language equivalent. (You may assume that definitions in the m324Adef.inc file are
available. Several instructions may be required. You can freely use general purpose registers).

(a) PORTC = 0xF3; (1 mark)










(b) UBRR1 = UBRR0; (2 marks)










(c) EEAR = 1992; (2 marks)











(d) EECR |= (1<









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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 12 of 22
Question 6. (continued)
(e) ADMUX &= ~(1<PORTB = (PORTD >> 2); (3 marks)






















(f) while (EECR & (1< ;
}
EECR |= (1<EECR |= (1<

















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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 13 of 22
Question 7. (13 marks)
The following is an edited extracted from Section 19.11 of the ATmega324A datasheet. You
will need to refer to this information when answering this question.
19.11.1. TC2 Control Register A
Name: TCCR2A
Offset: 0xB0


Bits 7:6 – COM2An: Compare Output Mode for Channel A [n = 1:0]
The table below shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast
PWM
mode.

Table 19-4. Compare Output Mode, Fast PWM
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected WGM22 = 1: Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match, set OC2A at BOTTOM, (non-inverting mode)
1 1 Set OC2A on Compare Match, clear OC2A at BOTTOM, (inverting-mode)

Note: A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case the
compare
match is ignored, but the set or clear is done at BOTTOM.

Bits 5:4 – COM2Bn: Compare Output Mode for Channel B [n = 1:0]
The table below shows the COM2B[1:0] bit functionality when the WGM0[2:0] bits are set to fast
PWM
mode.

Table 19-7. Compare Output Mode, Fast PWM
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Reserved
1 0 Clear OC2B on Compare Match, set OC2B at BOTTOM, (non-inverting mode)
1 1 Set OC2B on Compare Match, clear OC2B at BOTTOM, (inverting-mode)

Note: A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the
Compare Match is ignored, but the set or clear is done at TOP.

Bits 1:0 – WGM2n: Waveform Generation Mode [n = 1:0]
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation is to be used. Modes of operation supported by the Timer/Counter unit are: Normal
mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width
Modulation (PWM) modes.






Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 14 of 22
Table 19-9. Waveform Generation Mode Bit Description

Note:
1. MAX = 0xFF
2. BOTTOM = 0x00

19.11.2. TC2 Control Register B
Name: TCCR2B
Offset: 0xB1


Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode.

Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.

Bit 3 – WGM22: Waveform Generation Mode
Refer to TCCR2A.

Bits 2:0 – CS2[2:0]: Clock Select 2 [n = 0..2]
The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 19-10. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkI/O/1 (No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/32 (From prescaler)
1 0 0 clkI/O/64 (From prescaler)
1 0 1 clkI/O/128 (From prescaler)
1 1 0 clkI/O/256 (From prescaler)
1 1 1 clkI/O/1024 (From prescaler)
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.

Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 15 of 22
Question 7. (continued)
(a) With a diagram and appropriate symbols, define the terms “frequency” and “duty cycle”
in relation to pulse width modulation (PWM). (2 marks)










(b) Briefly explain one use of PWM in the context of microcontroller applications (3 marks)











(c) Write an assembly language routine for the Atmega324A microcontroller to obtain a
PWM signal with the following specifications: Fast PWM and non-inverting mode, PWM
output to be obtained on OC2A pin (port D, pin 7), pre-scalar of 32 for clock division.

(8 marks)

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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 16 of 22
Question 8. (8 marks)
Consider the following AVR ATmega324A assembly language module and answer the
questions on the following page.
.include “m324Adef.inc”
.equ INPUT_BUFFER_SIZE = 260
.equ NEWLINE = 15

.cseg
charconstants: .DB NEWLINE
.dseg
input_buffer: .BYTE INPUT_BUFFER_SIZE
bytes_in_input_buffer: .BYTE 1
input_insert_pos: .BYTE 1
.cseg
uart_get_char:
lds r24, bytes_in_input_buffer
tst r24
breq uart_get_char
save_interrupt_status:
in r18, SREG
andi r18, 0x80
cli
lds r24, input_insert_pos
lds r19, bytes_in_input_buffer
ldi r25, 0
sub r24, r19
sbc r25, r1
brpl extract_char
extract_char_and_wrap_buffer:
lds ZL, input_insert_pos
lds r24, bytes_in_input_buffer
ldi ZH, 0
sub ZL, r24
sbc r31, r1
subi ZL, 255-low(input_buffer-INPUT_BUFFER_SIZE)
sbci ZH, 255-high(input_buffer-INPUT_BUFFER_SIZE)
ld r24, Z
jmp decrement_buffer_count
extract_char:
lds ZL, input_insert_pos
lds r24, bytes_in_input_buffer
ldi ZH, 0
sub ZL, r24
sbc ZH, r1
subi ZL, 255-low(input_buffer)
sbci ZH, 255-high(input_buffer)
ld r24, Z
decrement_buffer_count:
lds r24, bytes_in_input_buffer
subi r25, 1
sts bytes_in_input_buffer, r25
tst r18
breq done
sei
done:
ldi r25, 0
ret



Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 17 of 22
Question 8. (continued)
(a) What is the overall size (in instruction words) of the code segment for this module?
(1 mark)




(b) What is the overall size (in bytes) of the data segment for this module? (1 mark)




(c) The module shown above (which we will now call module C) is linked with three other
modules (A, B and D) with code and data segment sizes as shown:

Module Code segment size
(instruction words)
Data segment size
(bytes)
A 65 47
B 57 35
D 79 34

If the modules are linked in order A, B, C and D starting from code segment address 0x3E
(62 decimal) and data segment address 0x100 (256 decimal), determine the code and data
segment relocation constants (in decimal) for all modules. (4 marks)

Module A Module B Module C Module D
Code Segment Relocation Constant
Data Segment Relocation Constant

(d) After linking as described in (c), at what memory address (in decimal) will the variable
bytes_in_input_buffer be found? (1 mark)




(e) After linking as described in (c), at what instruction word address (in decimal) will the
instruction at label extract_char be found? (1 mark)














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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 18 of 22
Question 9. (10 marks)
(a) The Western Digital Ultrastar HUS728T8TALN6L4 hard drive has the following
specifications:
Nominal Capacity: 8TB (1TB = 1012 bytes)
Sector size: 4096 bytes
Rotational speed: 7200 RPM
Max Sustained transfer rate: 255MB/s (1MB = 106 bytes)
Average seek time (typical): 8.0ms (read) / 8.6ms (write)

The hard drive is formatted with a file system that has a block size of 16kB (16,384 bytes)
and currently contains 1,600,000 files of various sizes which occupy 100,000,000 data
blocks.
i) What is the average access time when reading from the disk? (Show your working.)
(2 marks)










ii) How much total space within the 100,000,000 allocated data blocks is likely to be
wasted (i.e. not used for storing data)? (Show your working. Express your answer in
kB, where 1kB=1024 bytes). (2 marks)










iii) If the file system overhead is 4% of the total disk capacity, how many additional files
each of size 100kB (100 x 1024 bytes) could be saved on the disk? (Show your
working.)
(2 marks)










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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 19 of 22
Question 9. (continued)

(b)
i) Briefly explain the difference between synchronous and asynchronous serial
communication, identifying at least one similarity and one difference between the
two. (2 mark)














ii) If a Universal Asynchronous Receiver and Transmitter (UART) sends the 8-bit data
0xA5 with “even parity”, show how the parity bit can detect single bit errors
(2 marks)



























END OF EXAMINATION PAPER
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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
Page 20 of 22
This page is provided for rough or additional working and will not be marked unless an earlier
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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
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Semester One Final Examinations, 2021 CSSE2010 / CSSE7201 Introduction to Computer Systems
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