Instruction Set Architecture
and Datapath
Antonia Zhai
Department Computer Science and Engineering
University of Minnesota
http://www.cs.umn.edu/~zhai
CSCI 5204 / EE 5364
Instruction Set Architecture
Operating System
Silicon
Users
Instruction Set Architecture
Applications
Compilers
Firmware
Processor I/O System
Datapath & Control
Digital Design
Circuit Design
Layout & Fab
Objective
• Design Processor for MIPS Subset
• Initial Design
• One instruction at a time
• Single cycle per instruction
• Refined Design
• 5-stage pipeline, Similar to early RISC processors
• Goal: approach 1 cycle per instruction but with shorter
cycle time
Outline
• Datapath
• Control
CPU Overview
Hardware Units
Storage
• Instruction Memory
• Fetch 32-bit instructions
• Data Memory
• Load / store 32-bit data
• Register Array
• Storage for 32 integer registers
• Two read ports: can read two registers at once
• Single write port
Functional Units
• +4 PC incrementor
• ALU Arithmetic and logical instructions; branch testing
• Addr calculation Jump destination calculation
Adding Multiplexers
n Can’t just join
wires together
n Use multiplexers
Adding Control
Sequential Elements
• Register: stores data in a circuit
• Uses a clock signal to determine when to
update the stored value
• Edge-triggered: update when Clk changes from
0 to 1
D
Clk
Q
Clk
D
Q
Sequential Elements
• Register with write control
• Only updates on clock edge when write control
input is 1
• Used when stored value is required later
D
Clk
Q
Write
Write
D
Q
Clk
Clocking Methodology
• Combinational logic transforms data during
clock cycles
• Between clock edges
• Input from state elements, output to state
element
• Longest delay determines clock period
Instruction Fetch
32-bit
register
Increment by
4 for next
instruction
R-Format Instructions
• Read two register operands
• Perform arithmetic/logical operation
• Write register result
Load/Store Instructions
• Read register operands
• Calculate address using 16-bit offset
• Use ALU, but sign-extend offset
• Load: Read memory and update register
• Store: Write register value to memory
Branch Instructions
• Read register operands
• Compare operands
• Use ALU, subtract and check Zero output
• Calculate target address
• Sign-extend displacement
• Shift left 2 places (word displacement)
• Add to PC + 4
• Already calculated by instruction fetch
R-Type/Load/Store Datapath
Branch Instructions
Just
re-routes
wires
Sign-bit wire
replicated
Composing the Elements
• First-cut data path does an instruction in
one clock cycle
• Each datapath element can only do one
function at a time
• Hence, we need separate instruction and data
memories
• Use multiplexers where alternate data
sources are used for different instructions
Full Datapath
Outline
• Datapath
• Control
ALU Control
• ALU used for
• Load/Store: F = add
• Branch: F = subtract
• R-type: F depends on funct field
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR
ALU Control
• Assume 2-bit ALUOp derived from opcode
• Combinational logic derives ALU control
opcode ALUOp Operation funct ALU function ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111
The Main Control Unit
• Control signals derived from instruction
0 rs rt rd shamt funct
31:26 5:025:21 20:16 15:11 10:6
35 or 43 rs rt address
31:26 25:21 20:16 15:0
4 rs rt address
31:26 25:21 20:16 15:0
R-type
Load/
Store
Branch
opcode always
read
read,
except
for load
write for
R-type
and load
sign-extend
and add
Datapath With Control
R-Type Instruction
Load Instruction
Branch-on-Equal Instruction
Implementing Jumps
• Jump uses word address
• Update PC with concatenation of
• Top 4 bits of old PC
• 26-bit jump address
• 00
• Need an extra control signal decoded from
opcode
2 address
31:26 25:0
Jump
Datapath With Jumps Added