IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012 1183
On the Switching Parameter Variation of Metal Oxide
RRAM—Part II: Model Corroboration
and Device Design Strategy
Shimeng Yu, Student Member, IEEE, Ximeng Guan, Member, IEEE, and H.-S. Philip Wong, Fellow, IEEE
Abstract—Using the model developed in Part I of this two-part
paper, the simulated dc sweep and pulse transient characteristics
of a metal oxide resistive random access memory cell are corrobo-
rated with the experimental data of HfOx memory. Key switch-
ing features such as the abrupt SET process, gradual RESET
process, current fluctuation in the RESET process, and multilevel
resistance state distributions are captured by the simulation. The
current fluctuation in the RESET process is caused by the com-
petition between the simultaneous oxygen vacancy recombination
and generation processes. The origin of the high-resistance state
variation and the tail bit problem are attributed to the variation
of the tunneling gap distances and the stochastic nature of new Vo
generation in the tunneling gap region, respectively. The use of the
write–verify technique and a bilayer oxide structure are proposed
to achieve a tighter resistance distribution.
Index Terms—Parameter fluctuation, resistive random access
memory (RRAM), resistive switching, switching uniformity, tail
bit, variability.
I. INTRODUCTION
THE METAL oxide resistive random access memory(RRAM) is extensively studied as a competitive candidate
for future nonvolatile memory applications due to its simple
structure, fast switching speed, great scalability, and compati-
bility with silicon complementary metal–oxide–semiconductor
technology [1]–[3]. Among dozens of switching oxide ma-
terials, NiO- [4], WOx- [5], HfOx- [6], [7], TaOx- [8], [9],
and AlOx [10]-based memory devices have shown excellent
reliability, including long endurance and stable retention at
elevated temperature. A 4-Mb macro chip based on HfOx
memory has been demonstrated [11]. However, the key obstacle
for metal oxide RRAM to becoming mature for large-scale
manufacturing is the relatively poor control of switching unifor-
Manuscript received September 25, 2011; accepted January 10, 2012. Date
of publication February 17, 2012; date of current version March 23, 2012.
This work was supported in part by the member companies of the Stanford
Nonvolatile Memory Technology Research Initiative (NMTRI), the National
Science Foundation (NSF, ECCS 0950305), the Nanoelectronics Research Ini-
tiative (NRI) of the Semiconductor Research Corporation through the NSF/NRI
Supplement to the NSF NSEC Center for Probing the Nanoscale (CPN), and the
MSD and the C2S2 Focus Center, two of the six research centers funded under
the Focus Center Research Program (FCRP), a Semiconductor Research Cor-
poration subsidiary. The work of S. Yu was supported by the Stanford Graduate
Fellowship. The review of this paper was arranged by Editor V. R. Rao.
The authors are with the Center for Integrated Systems and Department of
Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail:
simonyu@stanford.edu; ximeng@stanford.edu; hspwong@stanford.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2012.2184544
mity. Significant parameter fluctuations exist in the switching
voltages and the resistance distributions, which include tempo-
ral fluctuations (cycle to cycle) and spatial fluctuations (device
to device). A large memory array usually contains noticeable
tail bits in the resistance distribution [12], which remarkably
reduces the resistance window and therefore imposes a great
challenge to realizing the multilevel capability of the metal
oxide RRAM technology.
The origin of the variations in the resistive switching is
not well understood yet, despite the fact that the variations
are observed in all RRAM reported. Phenomenological models
such as the network of random circuit breakers [13] have been
applied to the unipolar RRAM devices. In this paper, this
problem is studied for the metal-oxide-based bipolar RRAM
devices. Here, unipolar means the set from the high-resistance
state (HRS) to the low-resistance state (LRS) and the reset from
LRS to HRS occur at the same voltage polarity, and bipolar
means the set and the reset occur at opposite voltage polarities.
Through the development of a physics-based stochastic simula-
tor to quantify the switching variations, we identify the major
sources of variations and fluctuations. Specifically in this paper,
we focus on the cycle-to-cycle variability in RRAM devices,
which is a more intrinsic problem than the device-to-device
variability, because the device-to-device variability depends on
the fabrication processes, and better uniformity control of the
processes may improve the device-to-device uniformity. For
example, a chemical–mechanical polish was adopted to smooth
the bottom electrode and improve the uniformity HfOx-based
RRAM devices in an array [6]. The obtained insights provide
guidelines for future device design and optimization against
the undesired switching parameter variations. In part I of the
paper [14], we describe the developed model, which includes
the trap-assisted-tunneling current solver and the stochastic
generation and recombination of oxygen vacancies (Vo).1 The
considerations and approximations to reproduce the switching
characteristics of a bipolar RRAM device are discussed. In
part II of the paper (the current paper), we corroborate the simu-
lation results with the experimental data of HfOx-based RRAM
devices [15], [16], such as the dc I–V switching characteristics
and pulse transient switching waveform, multilevel resistance
distribution, etc., with a focus on discussing the origin of the tail
bit problem and possible elimination methods such as the use of
the write-verify technique and a bilayer oxide device structure.
1In the subsequent discussions in this paper, Vo can represent a single oxygen
vacancy or multiple oxygen vacancies.
0018-9383/$31.00 © 2012 IEEE
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1184 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012
Fig. 1. (a) Simulated and (b) experimental I–V characteristics of HfOx
memory for different reset stop voltages. Abrupt SET and gradual RESET
processes are reproduced by the simulation.
II. EXPERIMENTS
TiN/HfOx/Pt bipolar RRAM devices were fabricated. Pt of
50 nm was first deposited by electron-beam evapora-
tion on a silicon substrate as the bottom electrode layer.
Then, 10 nm HfOx was deposited by atomic layer depo-
sition using tetrakis (ethylmethylamino) hafnium (TEMA-Hf
Hf[N(C2H5)(CH3)]4) and H2O as precursors at 220 ◦C. The
crossbar patterns with a 0.5× 0.5 μm2 active cell area were
defined by photolithography. Then, 50-nm TiN was deposited
by reactive sputtering and was lifted off as a top electrode layer.
The electrical measurements were performed with an Agilent
4156C semiconductor parameter analyzer, an Agilent 81101A
pulse generator, and a Tektronix DPO 4054 oscilloscope. The
bottom electrode (Pt) was grounded, and the signals were
applied to the top electrode (TiN) in all the measurements.
III. SIMULATION RESULTS AND CORROBORATION
WITH EXPERIMENTS
In Part I of the paper [14], we described a stochastic sim-
ulator that can produce the dc switching characteristics of a
bipolar RRAM device. Here, we present additional dc sweep
simulation results, as plotted in Fig. 1(a), which shows the
effect of different reset stop voltages on the HRS resistance. It
is shown that larger reset stop voltages lead to a higher HRS
resistance because more oxygen ions are driven back to the
Fig. 2. (a) Simulated and (b) experimental pulse transient current in the
RESET process. Current fluctuation is reproduced by the simulation. In (b),
the last current jump at the end of the pulse is deduced to be a new generation
of Vo in the gap region.
bulk oxide and result in a larger ruptured conductive filament
(CF) length, and the current in HRS is mainly modulated by the
tunneling gap distance, as explained in Part I of the paper [14].
The corresponding experimental data of our fabricated HfOx
memory are shown in Fig. 2(b). Experimentally, modulation
of the HRS resistance by controlling the reset stop voltages
is also reported by others for HfOx and other metal oxide
materials [17], [18], suggesting that it is a common property
of metal oxide RRAM devices that can enable the multilevel
storage capability. In addition to the HRS modulation property,
it is noticed that our dc sweep simulation result also captures
other detailed features present in an experimental measurement
such as a more abrupt transition in the SET process and a
more gradual transition in the RESET process. The abrupt
SET process is due to the positive feedback that increasing
current leads to raised temperature, thus larger Vo generation
probability and, in turn, higher current. The gradual RESET
process is due to the gradual dissolution of the CFs away from
the electrode. We also perform the simulation under a pulse
programming condition, and the RESET transient waveform
is reproduced, as plotted in Fig. 2(a). The corresponding ex-
perimental RESET transient waveform is shown in Fig. 2(b).
It is shown that a significant current fluctuation is present in
the RESET pulse transient waveform (it is also observable in
a dc RESET curve shown above). We track the Vo evolution
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YU et al.: ON THE SWITCHING PARAMETER VARIATION OF METAL OXIDE RRAM II 1185
Fig. 3. (a) Simulated and (b) experimental multilevel states achieved by
linearly increasing RESET pulse amplitude.
with the current evolution simultaneously and find that the
current jump corresponds to new Vo generation in the gap
region. Therefore, the current fluctuation during the RESET
process is caused by a competition between the simultaneous
Vo generation and recombination processes. Although the CFs
are partially ruptured, the high field present in the gap region
may also induce Vo generation. This is particularly prominent
in the beginning stage of the current drop when the gap size is
small and the field and temperature are both high. The generated
Vo in the gap tend to reconnect the ruptured filament with the
cathode, giving rise to a current jump. We have to point out
that the observed current fluctuation is not due to a random
telegraph-like noise current that is caused by the individual
hopping electron tunneling, because the noise current under
a small constant voltage on our sample is measured to be of
less than 10% fluctuation [19]. Therefore, the larger fluctuation
shown in the RESET transient waveform is indeed caused by
the change of Vo configuration. We further perform the simu-
lation for different pulse programming schemes for achieving
multilevel HRS. In one scheme, the pulsewidth is fixed, and the
pulse amplitude is linearly increased to achieve different HRS
resistances, as shown in Fig. 3(a) [the corresponding experi-
mental data are shown in Fig. 3(b)]. In an alternate scheme, the
pulse amplitude is fixed, and the pulsewidth is exponentially
increased, as shown in Fig. 4(a) [the corresponding experimen-
Fig. 4. (a) Simulated and (b) experimental multilevel states achieved by
exponentially increasing RESET pulsewidth.
tal data are shown in Fig. 4(b)]. It has been suggested [15]
that these two programming schemes are equivalent to achieve
similar multilevel HRS owing to the exponential voltage–time
relationship: the switching time exponentially decreases with
the increase in applied voltage [20]. Our simulation further
confirms that similar gap distances are achieved by the two
programming schemes for a particular HRS level: for the three
HRS levels shown in Figs. 5 and 7, the average gap distances
are 0.7, 1.5, and 2.2 nm, respectively.
IV. DISCUSSION ON THE SWITCHING UNIFORMITY
IMPROVEMENT STRATEGIES
Significant switching parameter variations have become the
major problem that hinders metal oxide RRAM from large-
scale manufacturing. In the literature, efforts have been reported
to improve the uniformity either through materials/device struc-
ture engineering, e.g., to stabilize the formation/rupture of CFs
by the local electric field enhancement effect through dopant
diffusion [21], ion implantation [22], or inserting nanocrystals
[23] into the bulk oxide. The good news is that with the down-
scaling of the cell size, the switching uniformity, particularly
the LRS resistance distribution, is noticeably improved due
to the direct confinement of the conduction paths, as illustrated
in the novel device structure [24] for a 50-nm NiO RRAM
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1186 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012
Fig. 5. Simulated HRS distribution after 1000 times pulse cycling. The
lognormal distribution is due to the Gaussian distribution of the average gap
distances. The tail bits are due to new Vo near the electrode generated at the
end of the pulse (see Fig. 2(b) for an experimental example of tail bit creation).
device. However, the HRS resistance distribution is still widely
spread even for this device [24] with a confined conduction
path. Even for a 10-nm HfOx RRAM device [25], the HRS
variation is still remarkable. The reason may be attributed to
the different origins of LRS and HRS resistance variations: For
LRS, the current level is approximately linearly proportional to
the number or the size of CFs; thus, the reduction of possible
filament paths effectively confines the active switching area and
thus reduces the variation. For HRS, the current level is almost
exponentially dependent on the ruptured CF length; thus, any
small variation of the tunneling gap distance may be magnified
to be a remarkable variation of the HRS resistance, and the
tunneling gap distance is not directly related to the area of the
filament paths. Therefore, in this paper, we mainly focus on the
HRS variation, which is expected to be an intrinsic problem
even for future ultrascaled RRAM devices. We perform the
pulse cycling simulation in a single device for 1000 times and
plot the HRS distribution in Fig. 5. A straight line in this plot
means a lognormal distribution of the HRS bits, which reflects a
Gaussian-like variation of the average tunneling gap distances.
At the same time, a noticeable tail of the distribution is shown
in the plot. We correlate these tail bits with their corresponding
Vo configuration and reveal that the tail bits correspond to the
existence of Vo in the gap region. As analyzed above, during the
RESET process, the recombination and generation processes
of Vo compete with each other; thus, there is a possibility that
a new Vo is created in the gap region, leading to the current
jump observed in the transient current waveform. If the Vo
generation occurs in the middle of a programming pulse, it
has the chance to be recombined again with the mobile oxygen
ions. However, if the Vo generation occurs just at the end of a
programming pulse, it has no chance to be recombined again
since the pulse is withdrawn afterward [see the experimentally
Fig. 6. Simulated LRS and HRS distributions with the write–verify technique.
The purpose of multiple RESET pulses is to decrease the probability to get a
new Vo generation at the end of a single pulse. With a maximum of three trials,
above 99.9% HRS meet the criterion (1 MΩ). However, the over-RESET bits
may in turn cause more tail bits of LRS, which is undesired.
observed last current jump in Fig. 2(b)]. Therefore, Vo are left
in the gap region and act as a bridge for the electron tunnel
from the electrode to the residual of the CFs. To remove the
tail bits in HRS, the write–verify technique (write the cell first
and then read; if the cell resistance does not meet the resistance
criterion, write it again [26]) is usually used. The effectiveness
of the write–verify technique is illustrated by the simulation
results shown in Fig. 6. A maximum of three trials is able to
make 99.9% HRS bits meet the criterion. However, it is noticed
that the write–verify technique would introduce over-RESET
bits in HRS, which, in turn, may cause more tail bits (with
higher resistance than targeted) in LRS since the over-RESET
makes it harder for the CFs to reconnect with two electrodes
again. Of course, we can also use the write–verify technique
for the SET process to reduce the tail bits in LRS. However, the
cost of write–verify is very expensive because it decreases the
writing speed and increases the energy consumption. Therefore,
it is desirable to solve the problem through a combination of
device structure innovation and programming technique. We
propose using a bilayer oxide structure with a buffer oxide layer
that has a larger oxygen ion migration barrier than the active
switching oxide layer (see Fig. 7). The idea is to confine the
location of resistive switching by completely rupturing the CFs
in the active switching layer since the oxygen ion migration
would stop at the interface of the two layers due to a larger
migration barrier in the buffer layer. By tuning the active oxide
layer thickness, the over-RESET bits are eliminated, which,
in turn, reduce the tail bits in LRS. The results of simulating
such a structure are shown in Fig. 7. However, the bilayer
structure does not help reduce the tail bits in HRS because
the new Vo generation problem is still present, and actually,
it is more serious due to the reduced resistance window for
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YU et al.: ON THE SWITCHING PARAMETER VARIATION OF METAL OXIDE RRAM II 1187
Fig. 7. Simulated LRS and HRS distributions of a bilayer structure. The buffer
layer has a larger oxygen migration barrier (1.2 eV) than the active layer (1 eV)
to confine the CF rupture. The total thickness remains the same (10 nm). It is
shown that a 1.5-nm active layer is effective for reducing the over-RESET bits
and the tail bits of LRS, but it does not help eliminate the tail bits of HRS.
Fig. 8. Simulated both uniform LRS and HRS distributions are achieved by
combining a bilayer structure with the write–verify technique.
the thinner active layer structure. Therefore, by combining the
bilayer structure with the write–verify technique, it is expected
to achieve both uniform LRS and HRS distributions, as sim-
ulated in Fig. 8. Experimentally, uniformity improvement has
been demonstrated in the bilayer structure, such as HfOx/AlOx
[27], [28] and HfOx/ZrOx [29]. The choice of the buffer layer
materials and the optimization of thickness of each layer need
further study in the future.
V. CONCLUSION
The dc sweep and pulse transient simulation results given by
the stochastic simulator developed in Part I of the paper [14]
are corroborated with the experimental data of HfOx memory.
Key switching features such as the abrupt SET process, gradual
RESET process, and current fluctuation in the RESET process
are captured by the simulation. The experimental multilevel
states achieved by different programming schemes are also
reproduced by the simulation. The origin of the HRS resistance
variations and the tail bit problem are attributed to the variations
of the tunneling gap distances and new Vo generation in the
ruptured CF region. The write–verify technique and a bilayer
oxide structure are proposed to achieve a tight distribution in
HRS and LRS resistances. This paper provides new under-
standing of the physical sources of the switching parameter
variation phenomenon in metal oxide RRAM and guidelines
for future device optimization. Furthermore, the developed
simulator set up a platform to study other properties of RRAM
devices such as retention [30], overshoot, etc., which will be our
future work.
REFERENCES
[1] R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox-based resis-
tive switching memories—Nanoionic mechanisms, prospects, and chal-
lenges,” Adv. Mater., vol. 21, no. 25/26, pp. 2632–2663, Jul. 2009.
[2] H. Akinaga and H. Shima, “Resistive random access memory (ReRAM)
based on metal oxides,” Proc. IEEE, vol. 98, no. 12, pp. 2237–2251,
Dec. 2010.
[3] S. Yu, B. Lee, and H.-S. P. Wong, “Metal oxide resistive switching mem-
ory,” in Functional Metal Oxide Nanostructures, J. Q. Wu, Ed. Berlin,
Germany: Springer-Verlag, 2011.
[4] I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park,
S. O. Park, H. S. Kim, I. K. Yoo, U.-I. Chung, and I. T. Moon, “Highly
scalable nonvolatile resistive memory using simple binary oxide driven
by asymmetric unipolar voltage pulses,” in IEDM Tech. Dig., 2004,
pp. 587–590.
[5] W. C. Chien, Y. R. Chen, Y. C. Chen, A. T. H. Chuang, F. M. Lee,
Y. Y. Lin, E. K. Lai, Y. H. Shih, K. Y. Hsieh, and C.-Y. Lu, “A forming-
free WOx resistive memory using a novel self-aligned field enhancement
feature with excellent reliability and scalability,” in IEDM Tech. Dig.,
2010, pp. 19.2.1–19.2.4.
[6] H. Y. Lee, Y. S. Chen, P. S. Chen, P. Y. Gu, Y. Y. Hsu, S. M. Wang, W. H.
Liu, C. H. Tsai, S. S. Sheu, P. C. Chiang, W. P. Lin, C. H. Lin, W. S. Chen,
F. T. Chen, C. H. Lien, and M.-J. Tsai, “Evidence and solution of over-
RESET problem for HfOx based resistive memory with sub-ns switching
speed and high endurance,” in IEDM Tech. Dig., 2010, pp. 19.7.1–19.7.4.
[7] J. Lee, J. Shin, D. Lee, W. Lee, S. Jung, M. Jo, J. Park, K. P. Biju,
S. Kim, S. Park, and H. Hwang, “Diode-less nano-scale ZrOx/HfOx
RRAM device with excellent switching uniformity and reliability for
high-density cross-point memory applications,” in IEDM Tech. Dig.,
2010, pp. 19.5.1–19.5.4.
[8] Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani,
S. Fujii, K. Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga,
Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa,
H. Sugaya, T. Takagi, R. Yasuhara, K. Horiba, H. Kumigashira, and
M. Oshima, “Highly reliable TaOx ReRAM and direct evidence of redox
reaction mechanism,” in IEDM Tech. Dig., 2008, pp. 1–4.
[9] M.-J. Lee, C. B. Lee, D. Lee, S. R. Lee, M. Chang, J. H. Hur, Y.-B. Kim,
C.-J. Kim, D. H. Seo, S. Seo, U.-I. Chung, I.-K. Yoo, and K. Kim, “A
fast, high-endurance and scalable non-volatile memory device made from
asymmetric Ta2O5−x/TaO2−x bilayer structures,” Nat. Mater., vol. 10,
no. 8, pp. 625–630, Jul. 2011.
[10] W. Kim, S. I. Park, Z. Zhang, Y. Yang-Liauw, D. Sekar, H.-S. P. Wong,
and S. Wong, “Forming-free nitrogen-doped AlOx RRAM with sub-μA
programming current,” in Proc. Symp. VLSI Technol., 2011, pp. 22–23.
[11] S.-S. Sheu, M.-F. Chang, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu,
C.-C. Kuo, Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee,
P.-Y. Gu, S.-M. Wang, F. T. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng,
H.-T. Wu, T.-K. Ku, M.-J. Kao, and M.-J. Tsai, “4 Mb embedded SLC
resistive-RAM macro with 7.2 ns read–write random-access time and
160 ns MLC-access capability,” in Proc. IEEE Tech. Dig. ISSCC, 2011,
pp. 200–202.
[12] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin,
W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen,
C. H. Lien, and M.-J. Tsai, “Highly scalable hafnium oxide memory
Authorized licensed use limited to: TUFTS UNIV. Downloaded on March 22,2023 at 20:48:25 UTC from IEEE Xplore. Restrictions apply.
1188 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012
with improvements of resistive distribution and read disturb immunity,”
in IEEE Tech. Dig. IEDM, 2009, pp. 1–4.
[13] S. C. Chae, J. S. Lee, S. Kim, S. B. Lee, S. H. Chang, C. Liu, B. Kahng,
H. Shin, D.-W. Kim, C. U. Jung, S. Seo, M.-J. Lee, and T. W. Noh, “Ran-
dom circuit breaker network model for unipolar resistance switching,”
Adv. Mater., vol. 20, no. 6, pp. 1154–1159, Mar. 2008.
[14] X. Guan, S. Yu, and H.-S. P. Wong, “On the switching parameter variation
of metal oxide RRAM—Part I: Physical modeling and simulation method-
ology,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172–1182,
Apr. 2012.
[15] S. Yu, Y. Wu, and H.-S. P. Wong, “Investigating the switching dynam-
ics and multilevel capability of bipolar metal oxide resistive switching
memory,” Appl. Phys. Lett., vol. 98, no. 10, pp. 103 514-1–103 514-3,
Mar. 2011.
[16] S. Yu, Y. Wu, R. Jeyasingh, D. Kuzum, and H.-S. P. Wong, “An electronic
synapse device based on metal oxide resistive switching memory for
neuromorphic computation,” IEEE Trans. Electron Devices, vol. 58, no. 8,
pp. 2729–2737, Aug. 2011.
[17] L. Goux, Y.-Y. Chen, L. Pantisano, X.-P. Wang, G. Groeseneken,
M. Jurczak, and D. J. Wouters, “On the gradual unipolar and bipolar
resistive switching of TiN \ HfO2 \ Pt memory systems,” Electrochem.
Solid-State Lett., vol. 13, no. 6, pp. G54–G56, Apr. 2010.
[18] M. Terai, Y. Sakotsubo, S. Kotsuji, and H. Hada, “Resistance control-
lability of Ta2O5/TiO2 stack ReRAM for low-voltage and multilevel
operation,” IEEE Electron Device Lett., vol. 31, no. 3, pp. 204–206,
Mar. 2010.
[19] S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Understanding the
conduction and switching mechanism of metal oxide RRAM through
low frequency noise and AC conductance measurement and analysis,” in
IEDM Tech. Dig., 2011, pp. 12.1.1–12.1.4.
[20] S. Yu and H.-S. P. Wong, “A phenomenological model for the reset
mechanism of metal oxide RRAM,” IEEE Electron Device Lett., vol. 31,
no. 12, pp. 1455–1457, Dec. 2010.
[21] S. Yu, B. Gao, H. B. Dai, B. Sun, L. F. Liu, X. Y. Liu, R. Q. Han,
J. F. Kang, and B. Yu, “Improved uniformity of resistive switching behav-
iors in HfO2 thin films with embedded Al layers,” Electrochem. Solid-
State Lett., vol. 13, no. 2, pp. H36–H38, 2010.
[22] Q. Liu, S. Long, W. Wang, Q. Zuo, S. Zhang, J. Chen, and M. Liu,
“Improvement of resistive switching properties in ZrO2-based ReRAM
with implanted Ti ions,” IEEE Electron Device Lett., vol. 30, no. 12,
pp. 1335–1337, Dec. 2009.
[23] W.-Y. Chang, K.-J. Cheng, J.-M. Tsai, H.-J. Chen, F. Chen, M.-J. Tsai,
and T.-B. Wu, “Improvement of resistive switching characteristics in TiO2
thin films with embedded Pt nanocrystals,” Appl. Phys. Lett., vol. 95,
no. 4, pp. 042 104-1–042 104-3, Jul. 2009.
[24] B. Lee and H.-S. P. Wong, “Fabrication and characterization of nanoscale
NiO resistance change memory (RRAM) cells with confined conduction
paths,” IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 3270–3275,
Oct. 2011.
[25] B. Govoreanu, G. S. Kar, Y. -Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini,
I. P. Radu, L. Goux, S. Clima, R. Degraeve, N. Jossart, O. Richard,
T. Vandeweyer, K. Seo, P. Hendrickx, G. Pourtois, H. Bender, L. Altimime,
D. J. Wouters, J. A. Kittl, and M. Jurczak, “10 × 10 nm2 Hf/HfOx cross-
bar resistive RAM with excellent performance, reliability and low-energy
operation,” in IEDM Tech. Dig., 2011, pp. 31.6.1–31.6.4.
[26] M. Yin, P. Zhou, H. B. Lv, J. Xu, Y. L. Song, X. F. Fu, T. A. Tang,
B. A. Chen, and Y. Y. Lin, “Improvement of resistive switching in CuxO
using new RESET mode,” IEEE Electron Device Lett., vol. 29, no. 7,
pp. 681–683, Jul. 2008.
[27] S. Yu, Y. Wu, Y. Chai, J. Provine, and H.-S. P. Wong, “Characterization
of switching parameters and multilevel capability in HfOx/AlOx bi-layer
RRAM devices,” in Symp. VLSI-TSA, 2011, pp. 1–2.
[28] X. A. Tran, H. Y. Yu, B. Gao, J. F. Kang, X. W. Sun, Y.-C. Yeo,
B. Y. Nguyen, and M. F. Li, “Ni electrode unipolar resistive RAM
performance enhancement by AlOy incorporation into HfOx switching
dielectrics,” IEEE Electron Device Lett., vol. 32, no. 9, pp. 1290–1292,
Sep. 2011.
[29] J. Lee, E. M. Bourim, W. Lee, J. Park, M. Jo, S. Jung, J. Shin, and
H. Hwang, “Effect of ZrOx/HfOx bilayer structure on switching
uniformity and reliability in nonvolatile memory applications,”
Appl. Phys. Lett., vol. 97, no. 17, pp. 172 105-1–172 105-3,
Oct. 2010.
[30] S. Yu, Y. Y. Chen, X. Guan, H.-S. P. Wong, and J. A. Kittl, “A Monte
Carlo study of the low resistance state retention of HfOx based resistive
switching memory,” Appl. Phys. Lett., vol. 100, no. 4, pp. 043507-1–
043507-4, Jan. 2012, to be published.
Shimeng Yu (S’10) received the B.S. degree from
Peking University, Beijing, China, in 2009 and the
M.S. degree from Stanford University, Stanford, CA,
in 2011. He is currently working toward the Ph.D.
degree with the Department of Electrical Engineer-
ing, Stanford University.
He had a summer internship at IMEC, Leuven,
Belgium, in 2011. He has first-authored one book
chapter of Functional Metal Oxide Nanostructures
(Springer, 2011) and has authored or coauthored
tens of papers appearing in the IEEE International
Electron Devices Meeting, IEEE TRANSACTIONS ON ELECTRON DEVICES,
IEEE ELECTRON DEVICE LETTERS, Applied Physics Letters, Nanotechnology,
etc. He also serves as an active reviewer for these journals. His past research
activities include the simulation of the parameter fluctuation in nanoscale
transistors and SRAM cells. He has been working on the fabrication, charac-
terization, and modeling of the emerging resistive switching memory devices
and their applications for neuromorphic computation system since 2008.
Mr. Yu was the recipient of the Stanford Graduate Fellowship in 2009–2012
and the IEEE Electron Devices Society Masters Student Fellowship in 2010.
Ximeng Guan (S’06–M’11) received the B.E. and
Ph.D. degrees (with honors) from Tsinghua Univer-
sity, Beijing, China, in 2005 and 2010, respectively.
He is currently a Postdoctoral Scholar with the
Stanford Nanoelectronics Group, Stanford Univer-
sity, Stanford, CA. He has authored or coauthored 24
journal and conference papers, covering the topics of
quantum transport, band structure, strain, III–V de-
vice channels, carbon-based resistive memory, tun-
neling FETs, and nanoscale contact interfaces. He
is currently working on the modeling of resistive
nonvolatile memory, energy-efficient electronic devices, and MOSFETs with
high-mobility channels. His research interests are in the modeling of nanoscale
electronic devices.
Dr. Guan was the recipient of the IEEE Electron Devices Society Ph.D.
Student Fellowship in 2009.
H.-S. Philip Wong (S’81–M’82–SM’95–F’01) re-
ceived the B.Sc.(Hons.) degree from the University
of Hong Kong, Pokfulam, Hong Kong, in 1982, the
M.S. degree from the State University of New York
at Stony Brook in 1983, and the Ph.D. degree from
Lehigh University, Bethlehem, PA, in 1988, all in
electrical engineering.
In 1988, he joined the IBM T. J. Watson Research
Center, Yorktown Heights, New York. In September
2004, he joined Stanford University, Stanford, CA,
as a Professor of electrical engineering. While at
IBM, he worked on charge-coupled device and CMOS image sensors, double-
gate/multigate MOSFETs, device simulations for advanced/novel MOSFETs,
strained silicon, wafer bonding, ultrathin-body silicon-on-insulators, extremely
short gate FETs, germanium MOSFETs, carbon nanotube FETs, and phase-
change memory. He held various positions from Research Staff Member to
Manager, and Senior Manager. While he was Senior Manager, he had the
responsibility of shaping and executing IBM’s strategy on nanoscale science
and technology, as well as exploratory silicon devices and semiconductor tech-
nology. His research interests are nanoscale science and technology; semicon-
ductor technology; solid-state devices; electronic imaging; exploration of new
materials, novel fabrication techniques, and novel device concepts for future
nanoelectronics systems; and explorations into circuits and systems that are
device driven. Novel devices often enable new concepts in circuit and system
designs. His current research interests include carbon nanotubes, semiconduc-
tor nanowires, self-assembly, exploratory logic devices, nanoelectromechanical
devices, novel memory devices, and biosensors.
Prof. Wong served on the IEEE Electron Devices Society (EDS) as an elected
Administrative Committee Member from 2001 to 2006. He served on the IEEE
International Electron Devices Meeting Committee from 1998 to 2007 and was
the Technical Program Chair in 2006 and the General Chair in 2007. He served
on the International Solid-State Circuits Conference Program Committee from
1998 to 2004 and was the Chair of the Image Sensors, Displays, and MEMS
Subcommittee from 2003 to 2004. He serves on the Executive Committee of
the Symposia of VLSI Technology and Circuits. He was the Editor-in-Chief
of the IEEE TRANSACTIONS ON NANOTECHNOLOGY during 2005–2006. He
has been a Distinguished Lecturer of EDS since 1999 and was a Distinguished
Lecturer of the Solid-State Circuit Society during 2005–2007.
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