CSSE3010 - Embedded Systems Design and Interfacing Stage 4
CSSE3010 Stage 4
FreeRTOS Introduction
(Closed Shoes MUST BE Worn in the labs)
1 Assessment
• Git due 4pm Monday in week 8 .
• Course Marks: 10%
• Electronic Course Profile Pass Hurdle: Optional Submission. Best 3 out of 4 Stages
used to calculate total Stage mark.
2 Resources
• Nucleo platform
• Joystick
• OLED
• Logic Analyzer (AD2)
3 Structure
Your final stage code must be titled main.c and saved in your s4 folder.
PATH: csse3010/repo/s4
Listed below are the required mylib libraries, that you will need to develop for this stage.
They should be saved in your mylib/ folder.
PATH: csse3010/repo/mylib/.
• OLED Register and Task Library
• Joystick Register and Task Library
• Sysmon Register Library
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
4 Preparation
It is recommend that you attempt the following labs first before starting this stage. The
labs or lab quizzes are not assessed in this stage.
• Lab 5.1 - FreeRTOS Introduction
• Lab 2.9 - I2C
• Lab 3.7 - OLED Display
• Lab 1.5 - Waveforms Diagram
4.1 Black Board Quiz
The Black Board quiz contains helpful questions related to this stage. It must be completed
and submitted on BlackBoard.
5 Workbook Tasks
Follow the workbook guidelines on Blackboard. You need to use the hardware and flow chart
templates. Each task that you create must have an associated flow chart.
NOTE: If your design is modified, all relevant workbook diagrams should be also be up-
dated to reflect the changes. You are also required to draw conclusions of the result of your
stage implementation for your week 8 session.
6 Work Diagram Tasks
Follow the work diagram guidelines on Blackboard. You need to use the hardware, flow
chart and state diagram templates. You must drew the hardware schematic for this stage.
You must draw and submit the flow chart for the cyclic executive of the Task 2 task used
in DT3 and the OLED mylib control task. DO NOT draw the FreeRTOS Task FSM.
No other flow charts or state diagrams are to be submitted. You are encourage to draw flow
charts for the other mylib register functions.
7 Design Tasks
A system monitor is commonly used tool used to view the current state of operating system
tasks. A simple system monitor can be implemented using GPIO pins and a logic analyser.
Each time a task executes, it will set a GPIO pin high and low. This can be seen in Figure 1
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
Figure 1: System Monitor showing three Tasks executing.
Implement and test a system monitor. You must ensure that your mylib library is used.
Update your sourcelib before continuing.
7.1 mylib Setup
YouMUST FOLLOW the Template Code given in the sourcelib/examples/templates/mylib
folder. Your mylib code must meet the guidelines specified in the mylib and plat-
form build guides, on Blackboard. You MUST create the right file structure in
the mylib git folder.
You will create mylib library files for the system monitor (sysmon). Refer to the sysmon
mylib specifications, on Blackboard.
7.2 Design Task 1: Task Creation and System monitor
This task must be completed before commencing the remaining tasks.
This task involves creating tasks and examining how task priorities affect a task’s opera-
tion. Create three tasks in main.c and assign the priorities listed in Table 1. Implement a
system monitor to view the occurrence of each task, by setting a GPIO pin high when a task
executes and low, when the task goes idle (first line the infinite for loop and last line in the
for loop). This allows the logic analyser to be used to view the execution and idle period of
each task. Section 8 shows the pins assigned to each logic analyser channel. Structure your
task 1-3 code to be similar to the pseudo code shown in Figure 2. NOTE: Task 3 should
NOT have any task delays.
1 void Task1 Task( void ) {
2
3 hardware init();
4
5 SXXXXXXX REG SYSMON CHAN0 CLR(); //Clear LA Channel 0
6
7 for (;;) {
8
9 task ENTER CRITICAL(); //Prevent interruption of
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
10 //Task Critical section.
11 SXXXXXXX REG SYSMON CHAN0 SET(); //Set LA Channel 0
12 BRD LEDToggle(); //Random instruction
13
14 vTaskDelay(3); //Extra Delay for 3ms
15 SXXXXXXX REG SYSMON CHAN0 CLR(); //Clear LA Channel 0
16
17 task EXIT CRITICAL();
18 }
19 }
Figure 2: Pseudo Code (Will NOT Compile)
Table 1: Task Priorities, Delays and System Monitor Pins
Task Priority Extra Task Delay Sysmon Channels
Task1 +2 3ms SXXXXXXX REG SYSMON CHAN0
Task2 +2 3ms SXXXXXXX REG SYSMON CHAN1
Task3 +2 DO NOT CALL vTaskDelay SXXXXXXX REG SYSMON CHAN2
FIRST, disable the idle task in FreeRTOSConfig.h (configUSE IDLE HOOK). Using the sys-
tem monitor, observe and record in your workbook screenshots printouts of the LA and a
brief written explanation, for the following:
1. Keep the priority of Task 1, Task 2 and Task 3 at priority +2 and note the effect, using
the system monitor.
2. Increase the priority of Task 3 to +4 (with Task 1 and 2 at priority +2) and note the
effect, using the system monitor.
3. Decrease the priority of Task 3 to +1 (with Task 1 and 2 at priority +2) and note the
effect, using the system monitor.
4. Keep the tasks priorities as specified in 3) and disable preemption in the FreeRTOSCon-
fig.h file and note the effect.
5. With preemption disabled, Task 1 & 2 at priority +2 and Task 3 priority to +1, modify
Task 3 (ignore Table 1 directive) , so that Task 1 and 2 can execute. Note what changes
you made. (Hint: what does a task delay do?)
You must use the waveforms template with the screenshots to create a submission for Black-
Board, as a single PDF, with your other work diagrams. The screenshots must be cropped
to show just the 3 system monitor outputs. You must be able to explain the observations in
each screenshot. You may also paste the screenshots in your workbook.
Note: When changing #define values, you must run make clean before running make.
To view the waveform on the LA, use a time base of 1ms/div.
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
Refer to examples/os/fr task and examples/os/fr sysmon examples. Also refer to http:
// www. freertos. org for the latest FreeRTOS task API.
7.3 Design Task 2: Task Control and FreeRTOS Configuration
Control the running of task 2, using task 3 with the joystick Z button. If the joystick Z
button is pressed, with task 2 running, it must then be deleted. If the joystick Z button
is pressed, with task 2 deleted, then it must be created. The running of task 2 should be
observed using the system monitor. You must use suitable FreeRTOS task create functions
e.g. vTaskDelete() xTaskCreate().
Hint: You may need to modify the FreeRTOSConfig.h and makefile to include the appropri-
ate heap. Check the FreeRTOS API documentation for details on how to use vTaskDelete()
xTaskCreate().
Use a the joystick Z button semaphore to signal task 3, to delete or create task 2. Use the
Joystick Z button to trigger an external interrupt. Modify the mylib joystick files with an
additional Joystick Z semaphore semaphore. Refer to the task mylib guidelines. You should
not add an additional tasks or semaphores joystick mylib. Do not add any specific stage 4
functionality to the mylib file. A reminder that mylib files must only contain code functions
that can be reused and not re-written.
Task Stack Memory Memory configuration is managed in FreeRTOS using the FreeR-
TOSConfig.h and by including the appropriate memory heap model (.c file). Find the lowest
task stack memory value that task 1 can run on. What happens if a task has not enough
memory assigned?
7.4 Design Task 3: OLED Display
Use the OLED to display the string ′ >>′. Each time Task 2, completes the final delay,
the string must move by 5 pixel positions, to the right. The string should be drawn at the
left-side of the OLED display, when Task 2 starts. When the string reaches the right-side of
the OLED, it should wrap around and start again from the left-side. You must implement
the OLED mylib file. A reminder that mylib files must only contain code functions that can
be reused and should not contain any code specific to this Task.
Hint: Some tasks (e.g. OLED mylib control task) may have a high latency and if the cor-
responding priority is not high enough, it can be blocked from running, infinitely. Managing
task priorities is essential for reliable operation.
OLED Wiring The OLED must be wired as shown in lab 1.4 and must include the LA
test points. The OLED must NOT be directly connected to the board. The OLED cable
must be inserted into the breadboard and wires must be used to connect the OLED data
lines using the LA test points.
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
7.5 Design Task 4: OLED I2C SDA and SCL Signal Waveform
The OLED I2C SDA and SCL signal waveforms must be viewed and captured using the Logic
Analyzer with the corresponding I2C protocol analyzer. Capture and show the following
actions from the I2C Write multi-byte transactions between the board and the OLED, as
listed below. See also the Fig8-7, page 20 of the SSD1306 datasheet, on BlackBoard.
• Start (S)
• I2C (Slave) Address and Write bit
• Control byte
• One byte or more data
• Acknowledge (ACK)
• Stop (P)
You must use the waveform template (from Black Board) and show that all key parts of the
waveform. The entire waveform does not need to be shown (e.g. all the data bytes). Only
a small sub-section of the data sent, needs to be captured. The waveform template must be
uploaded to Black Board. The captured I2C SCL signal must be shown as a periodic square
wave.
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
8 Pin Assignments
NOTE: The pins listed here are Board Pins only. You must map them to the Processor
Pins using the Nucleo Pinout for your board.
8.1 Nucleo-F429
Board Pins Notes
D15 OLED SCL
D14 OLED SDA
A0 Joystick Pushbutton
D43 Sysmon Channel 0
D44 Sysmon Channel 1
D45 Sysmon Channel 2
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
9 Criterion
The stage demonstrations are marked according to the criterion outlined in the table below.
If you fail to demonstrate sufficient understanding and functionality in the specified marking
time you will not be allowed to repeat the stage. You must pass the pre-demo checks before
you are allowed to demo. All code assessed for the stage must be your own work.
9.0.1 Pre Demo Checks
The following criteria must be met before you are allowed to demo.
Check P/F
Your latest stage and mylib code must be in git.
Your git repository must be up to date with the lates version of sourcelib.
Your stage code must build without errors.
Your mylib and top comments are correctly filled out.
Failure to meet pre-demo checks will mean that you are not allowed to demo the stage.
9.0.2 Demo and Implementation Criterion
You must be able to combine all design tasks, into the same file and demo all design tasks,
without reprogramming your Nucleo. Note: You may be asked to make minor modifications
to your code by the assessor, during your demo, which must be passed.
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
Design Task 1: Task Creation and System monitor
1 or 0 Screenshot for condition 1 is shown and can be explained (else 0).
1 or 0 Screenshot for condition 2 is shown and can be explained (else 0).
1 or 0 Screenshot for condition 3 is shown and can be explained (else 0).
1 or 0 Screenshot for condition 4 is shown and can be explained (else 0).
1 or 0 Screenshot for condition 5 is shown and can be explained (else 0).
Design Task 2: Task Control and FreeRTOS Configuration
0 There is no attempt to call vTaskCreate() or vTaskDelete() on a regis-
tered joystick press.
1 The joystick press causes a semaphore call in an ISR, an attempt is
made to call the vTaskDelete() and xTaskCreate() functions based on
the status of this semaphore, but errors occur.
2 The joystick press causes a semaphore call in an ISR, an attempt is
made to call the vTaskDelete() and xTaskCreate() functions based on
the status of this semaphore and it correctly works.
Design Task 3: OLED Display
0 OLED display cannot function or the OLED mylib is not used or imple-
mented.
1 OLED display functions but errors occur with the display of the string
or the string display does not advance.
2 OLED display functions correctly and the string does advance but errors
in the refresh rate (freezes) or display errors occur (wrong character).
3 OLED display functions correctly and the string advances but does not
wrap around.
4 OLED display functions correctly and the string advances and wrap
around and the refresh rate .
Design Task 4: OLED I2C SDA/SCL Signal Waveform
0 OLED I2C waveforms diagram is not submitted or attempted or the
viewable resolution of the waveforms is too small and cannot be distin-
guished as a square wave signal or the LA I2C protocol analyzer has not
been used.
1 OLED I2C waveforms diagram with either SDA or SCL, is shown but
not explained or not explained sufficiently. The viewable resolution of
the waveforms is sufficient and can be distinguished as a square wave
signal and the LA I2C protocol analyzer has been used.
2 OLED I2C waveforms diagram (both SDA and SCL) is shown and ex-
plained well. The viewable resolution of the waveforms is sufficient and
can be distinguished as a square wave signal and the LA I2C protocol
analyzer has been used.
CSSE3010 - Embedded Systems Design and Interfacing Stage 4
Sysmon, OLED and Joystick Task mylib
0 Sysmon, OLED and joystick Task mylib drivers are not implemented.
1 Sysmon, OLED and joystick Task mylib drivers are partially imple-
mented or errors occur with both driver.
2 Sysmon, OLED and joystick Task mylib drivers are fully implemented
but errors occur with one driver.
3 Sysmon, OLED and joystick Task mylib drivers are fully implemented
and operate correctly.
Task Stack Usage and Delay
0 No Task stack usage or delays listed in workbook.
1 All Task stack usage or delays listed in workbook.
Workbook Tasks
0 One or more workbook tasks have not been completed.
1 All workbook tasks completed.
Submitted Workbook Flow Charts
0 Flow charts are not attempted, or are incorrect.
1 Flow charts are correct but do not follow the correct syntax.
2 Flow charts are correct and follow the correct syntax.
Workbook Schematic
0 Hardware schematic diagram has not been completed.
1 Hardware schematic diagram is complete.
Quiz
0 Not submitted.
1 Less than half of the questions are correct.
2 Half or more than half of questions are correct.
Late Penalty
-10% per day up to 7 calendar days.