Distributed Control Systems
EEE8151
(Completed Version)
Module Leader: Dr Mohammed Elgendy
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Contents
Chapter 1 Introduction to Distributed Control Systems ....... 1
1.1 Aims ............................................................................................................. 1
1.2 Introduction .................................................................................................. 1
1.2.1 The Factory as a Control System ......................................................... 2
1.2.2 Communication in a Factory Environment ............................................ 4
1.2.3 Production Control Components ........................................................... 5
1.2.4 Flexible Manufacturing Systems ........................................................... 5
1.2.4.1 The centralised controller cell ............................................................... 5
1.2.4.2 The networked cell ................................................................................ 6
1.2.4.3 Definition of a Distributed Control System ............................................ 7
1.3 Introduction to SCADA Systems .................................................................. 8
1.3.1 Classic SCADA systems (old!) .............................................................. 9
1.3.2 Modern SCADA systems (state of the art!) ......................................... 11
1.3.2.1 System Implementation ...................................................................... 12
1.3.2.2 SCADA Software ................................................................................ 13
1.3.3 Remote Terminal Unit Hardware ........................................................ 14
1.3.3.1 Power Supply ...................................................................................... 14
1.3.3.2 Central Processing Unit ...................................................................... 14
1.3.3.3 Memory ............................................................................................... 14
1.3.3.4 Analogue Inputs .................................................................................. 15
1.3.3.5 Analogue Outputs ............................................................................... 18
1.3.3.6 Digital Inputs and Outputs ................................................................... 18
1.3.3.7 Communication Interfaces .................................................................. 18
1.3.3.8 A rack / enclosure ............................................................................... 18
1.4 Microprocessor and System Measurements .............................................. 19
1.4.1 Microprocessor ................................................................................... 19
Off-Line Processing ........................................................................................... 19
Real Time Processing ....................................................................................... 19
1.4.1.1 Typical task execution within a microprocessor .................................. 20
1.4.1.2 Interrupts ............................................................................................. 20
1.4.1.3 Circular Buffering ................................................................................ 22
1.4.1.4 SDL Exercise 1: Choosing a DSP Processor ...................................... 24
1.4.2 System Measurements – effect of digitisation ..................................... 27
1.4.2.1 Signal Amplification ............................................................................ 27
1.4.2.2 Sampling Process ............................................................................... 28
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1.4.2.3 Analogue to Digital Conversion ........................................................... 29
1.4.2.4 Minimising the measurement error ..................................................... 31
1.4.2.5 SDL Exercise 2: ADC measurement issues. ....................................... 32
Chapter 2 Communication Medium: Networks ........................................... 33
2.1 Aims ........................................................................................................... 33
2.2 Networking and its Benefits........................................................................ 33
2.3 Data Transmission ..................................................................................... 34
2.4 Interconnection Technology ....................................................................... 35
2.5 Sources of Noise and Signal Distortion ...................................................... 37
2.6 Networking Topologies .............................................................................. 39
2.6.1 Bus Network ....................................................................................... 39
2.6.2 Ring Network ...................................................................................... 39
2.6.3 Star Network ....................................................................................... 40
2.6.4 Hub Network ....................................................................................... 40
2.6.5 Bus Repeaters .................................................................................... 41
2.7 Frame Concept .......................................................................................... 42
Example 1: General Data format ....................................................................... 43
Example 2: RS232 Format ................................................................................ 43
2.8 Medium Access Control ............................................................................. 44
2.8.1 Poll/Select ........................................................................................... 44
2.8.2 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) .. 45
2.8.3 Token Ring and Token Bus MAC ....................................................... 46
2.8.4 Slotted Ring ........................................................................................ 47
2.9 Error Checking Mechanisms ...................................................................... 49
2.9.1 Checksum ........................................................................................... 49
2.9.2 Parity Check ....................................................................................... 51
2.9.3 Block Parity Check .............................................................................. 53
2.9.4 Cyclic Redundancy Check (CRC) ....................................................... 54
2.10 Practical Issues in Networking ................................................................... 58
2.10.1 Network Performance ......................................................................... 58
2.10.2 Line drivers – Common signal Standards ........................................... 60
TTL line driver ................................................................................................... 61
Current line driver .............................................................................................. 61
RS422 ............................................................................................................... 62
RS485 ............................................................................................................... 63
2.10.3 Data synchronisation .......................................................................... 64
Asynchronous Sampling ................................................................................... 65
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Synchronous Sampling ..................................................................................... 66
Chapter 3 Network Protocols: ISO Reference Model ................ 69
3.1 Aims ........................................................................................................... 69
3.2 Standards................................................................................................... 69
3.3 The ISO/OSI Reference Model .................................................................. 69
3.3.1 The General Framework of The OSI Reference Model....................... 70
3.3.2 Data Transfer ...................................................................................... 71
3.4 Details of the 7 Layers ............................................................................... 72
3.4.1 Application Layer ................................................................................ 73
3.4.2 Presentation Layer .............................................................................. 73
3.4.3 Session Layer ..................................................................................... 74
3.4.4 Transport Layer .................................................................................. 74
3.4.5 Network Layer ..................................................................................... 75
3.4.6 Data Link Layer ................................................................................... 75
3.4.7 The Physical Layer ............................................................................. 77
Chapter 4 CAN: Controller Area Network .......................... 78
4.1 Aims ........................................................................................................... 78
4.2 Introduction ................................................................................................ 78
4.3 CAN Specifications .................................................................................... 79
4.4 CAN ISO/OSI Reference Model. ................................................................ 79
4.5 CAN Physical Layer ................................................................................... 80
4.5.1 Non return to zero (NRZ) representation ............................................ 81
4.5.2 Bit Stuffing .......................................................................................... 82
4.5.3 Bit Timing Configuration...................................................................... 84
4.5.4 Configuring the Nominal Bit Time. ...................................................... 85
4.5.5 Physical Connection ........................................................................... 86
4.5.6 Standard Connectors .......................................................................... 87
4.6 CAN Bus Basic Operation .......................................................................... 88
4.7 CAN Data Link Layer ................................................................................. 89
4.7.1 Frame Formats ................................................................................... 90
4.7.2 Message Filtering ............................................................................... 93
4.7.3 Bus Arbitration .................................................................................... 93
4.7.4 Error Handling ..................................................................................... 94
4.8 CAN Hardware Implementations ................................................................ 96
4.8.1 CAN Controller Organisation .............................................................. 96
4.8.2 Basic CAN vs Full CAN Implementations ........................................... 99
4.9 Stand-alone versus Embedded CAN Controllers ..................................... 104
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4.9.1 Overview of the CAN Hardware Market ............................................ 105
4.10 CANopen ................................................................................................. 106
4.10.1 Re-look at the CAN ISO/OSI Reference Model. ............................... 106
4.10.2 Missing Layers .................................................................................. 106
4.10.3 CAN Application Layer ...................................................................... 108
4.10.4 CANopen Profiles ............................................................................. 109
i) CANopen device profiles ......................................................................... 109
ii) CANopen communication profile .............................................................. 110
4.10.5 4 Service primitives ........................................................................... 110
4.10.6 Application Layer services ................................................................ 111
4.10.7 Device Definition: The Object Dictionary ........................................... 115
i) Object Dictionary Structure ...................................................................... 115
ii) Object Dictionary Addressing ................................................................... 116
4.10.8 Communication Types ……………………………………………...117
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Chapter 1
Introduction to Distributed Control Systems
1.1 Aims
On completion of this chapter, you should;
➢ Have an appreciation of the impact of automated systems in modern manufacturing
processes.
➢ Have a basic knowledge of, and be able to define, what a Distributed Control System
is.
➢ Understand the main components and the general benefits of Distributed Control
Systems.
➢ Have a basic knowledge of SCADA systems.
➢ Understand the differences between SCADA and Distributed Control Systems.
➢ Understand the concept of real-time task execution within a microprocessor.
➢ Understand the effect of digitisation on system measurements.
➢ Have a basic knowledge of different types of memories and how to use them efficiently.
1.2 Introduction
Since the Introduction of computers into the manufacturing workplace, Information
Technology (IT) and Automation Systems have revolutionised the way in which
manufacturing industry operates. This applies to the general organisation and
procedures adopted by manufacturing industry as well as specific methods and
techniques of manufacture. These changes have brought about several benefits to
industry:
➢ A decrease in processing time
➢ A reduction in production costs. e.g. by reducing waste
➢ The production of better quality products - reducing the number of defective products
and lowering failure rates.
➢ It is now possible to replace workers in dangerous environments with machinery
However, this is not the complete story. Other advantages, which may be less direct
but often have greater impact in the longer term include:
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➢ A greater understanding of the manufacturing process, allowing easier identification of
bottle-necks.
➢ Better production scheduling, making maximum use of the production facilities.
➢ Greater flexibility in response to changes in design, customer requirements and
competition.
➢ Shorter 'lead times' in designing new products.
➢ Faster identification of faults in both product and processing machinery.
➢ Ability to identify deterioration in equipment before actual failure, reducing production
'down time'.
In a system that must be flexible, its individual components and processing systems
must also be flexible. They must be capable of changing their operational parameters,
tooling or processing operations at short notice, perhaps on a job to job basis. This is
where computer based automation comes into effect.
Computer systems imply programmability and decision making capability, i.e.
intelligence. Intelligent production systems, cells & work stations and even individual
cell components are at the heart of the flexible capability of advanced manufacturing
systems.
It is for these reasons that this new technology is considered an asset. However, as
engineers it is the technology that interests us, for business it will be the advantages
that the application of this technology can bring to production. This will be the driving
force in bringing the technology to the work place.
1.2.1 The Factory as a Control System
To maintain a successful and competitive manufacturing industry, knowledge in the
field of communication systems is crucial. Figure 1.1 shows a block diagram depicting
the multiple communication links that, in general, are in operation within a factory
environment. The communication link very much forms a control system consisting of
multiple feedback loops.
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Figure 1.1: Communication within a manufacturing plant
As can be seen from the diagram the factory and manufacturing system may be
thought of as a control system consisting of several feedback loops:
(1) Product design is based on externally obtained information
(2) Product design drives manufacturing efforts
(3) Manufacturing capabilities constrains and shapes product design
(4) Manufacturing requires materials input
(5) Manufacturing output is delivered outside via distribution and sales
(6) Marketing gathers internal and external information
(7) Marketing feedback shapes product design, manufacturing and sales
(8) Sales are fed through finance to corporate management
(9) Corporate management shapes product design decisions
This obviously requires communication at all levels between one part of the system
and the next.
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1.2.2 Communication in a Factory Environment
Communication in a factory environment consists of different networking levels. These
range from the simplest network inside a machine, to the network running around the
shop floor, the design room, the management, finance departments and corporate
level, where worldwide communication may be involved. It is certain that this
communication will involve the Internet. In fact the 21st century may see the advance
of a factory completely remotely controlled over the Internet from one central site
elsewhere in the world.
According to the International Standards Organisation, an automated
manufacturing system may be described as a three-level hierarchical model,
This model is shown in Figure 1.2.
DISCRETE PROCESS
SENSORS – temperature,
pressure, force etc
Operator Panels,
Data Logging,
SCADA
Drives, Sensors,
Valves,
Instrumentation
Control: I/O,
Alarms,
Interlocks,
Programming.
INFORMATION
CONTROL/AUTOMATION
Figure 1.2: Factory automation hierarchy
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As shown in Figure 1.2, a hierarchy of communication systems is required to meet the
needs of all the elements within a manufacturing environment.
Higher level networks are not suitable to implement the communication
mechanisms required in the shop floor. Similarly, lower level networks, such as
CAN protocols, could not possibly be used to perform tasks that require a lot
more than the simple interconnection of sensors and actuators on an
automation cell.
1.2.3 Production Control Components
Most equipment found in industry can be divided into four key categories:
➢ Process Control Equipment (Control/Automation Level) – programmable
devices which control processes. These include, industrial computers, PLCs,
specialist controllers for robots, CNC machines etc.
➢ Mechanical Components (Discrete Process Level) – conveyor belts,
linear/rotary axes controlled by motors, automated guided vehicles
➢ Actuators (Discrete Process Level) – these include electric motors,
pneumatic valves, pistons, maglev guides, and other similar devices which
perform operations.
➢ Sensors (Discrete Process Level) – these are used for obtaining
measurements and data from the environment. For example, the position of
mechanical components, testing the quality of products.
1.2.4 Flexible Manufacturing Systems
Programmable devices and controllers have given the industrial user the ability to
change the production cell simply by reprogramming the controller without having to
change the wiring to the individual sensors and actuators. As a result, the
manufacturing system is much more flexible. Furthermore, it has lowered system costs
by reducing the time spent having to reconfigure manufacturing cells to produce new
products. We will look at two types of flexible system.
1.2.4.1 The centralised controller cell
Figure 1.3 shows a system commonly known as a centralised control cell. Here, a
number of control devices are connected to a central control system. This central
controller is responsible for the overall operation of the cell. Each control device is
mounted in a different location within the production cell and may require a different
electrical interface to the controller.
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Electric
Drive
Bar Code
Scanner
Push Button
Panel
Position
Sensors
Input/Output
Devices
Motor
Starter
Controller
Figure 1.3: Typical centralised controller cell
As a result, there are several possible limitations to this configuration:
➢ Numerous wires must be run around the cell from component to controller.
➢ As cell complexity increases, so does the complexity of the wiring, increasing
costs and proving difficult to troubleshoot in the event of a fault.
➢ It may be difficult to connect all the wires to the controller simply because of the
physical size of the connectors.
➢ The centralised controller can be reprogrammed to meet changing production
needs but each cell must be re-programmed separately at the location of the
controller.
➢ If new sensors or actuators are needed for the cell additional work may be
needed to provide new interfaces to the controller (lots of interfaces available!).
1.2.4.2 The networked cell
To overcome the problems highlighted with the centralised controller system, a
network solution is now typically employed in modern automation industry. A common
approach is to employ a fieldbus solution, similar to that shown in Figure 1.4.
➢ A fieldbus is simply a commonly shared communication medium, to which all
devices and controllers may be connected. It then enables efficient
communication between all the components of the production cell.
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Network
Controller
Electric
Drive
Bar Code
Scanner
Push Button
Panel
Position
Sensors
Device
Configuration
Input/Output
Devices
Motor
Starter
Figure 1.4: Typical networked controller cell
With the development of advanced IT systems and low cost microcontrollers with
integrated network capabilities; all control components, from simple switches to
complex systems such as electric drives, now have the capability to communicate with
each other.
This arrangement offers significant advantages over the centralised controller system.
➢ Normally only one set of communication wires plus power lines are needed.
➢ Typically only one connection to each component from the network, reducing
the overall wiring cost.
➢ All the components have a standard interface to the controller via the network.
New devices can be connected easily.
➢ Diagnostics and fault finding are simplified.
➢ The controller can operate over a greater geographical area.
This is the concept behind distributed control systems. A distributed control
system is a networked control system with a fieldbus at its heart. Several
industry standard fieldbuses exist. CAN®, Profibus® and Modbus® are examples
of popular fieldbus protocols currently available on the market and are currently
being used widely in the manufacturing industry.
1.2.4.3 Definition of a Distributed Control System
A distributed control system may be defined as follows:
A distributed control system is one composed of several autonomous intelligent
devices, which cooperate in achieving an overall goal. These intelligent devices
are capable of supporting processes and coordinating their activities, through
the exchange of information via means of a communication network
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1.3 Introduction to SCADA Systems
This section gives a broad overview of Supervisory Control and Data Acquisition
(SCADA) systems.
➢ Technically, a SCADA system is not a DCS!
Therefore, it is important to distinguish the difference between the two.
➢ Traditionally, in a SCADA system, the distance between the control system
location and the controlled plant was such that direct wired control was
impractical.
➢ In contrast, in a DCS, the data acquisition and control functions occur on a
number of distributed microprocessor based resources, which are situated near
to the device being controlled. Therefore, this allows for direct wired control.
➢
DCS SCADA
Measurement,
Process control,
Communication
between processes
Measurement,
telemetry,
Data strorage and
processing
So, why are we considering SCADA systems?
➢ The distinction between DCS and SCADA is now less apparent than in the past.
➢ Communication and microprocessor technology has advanced dramatically in
recent years (say 1990+), and the traditional boundary between the two has
become somewhat blurred. Each now includes features that the other
traditionally incorporated.
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DCS SCADA
Measurement, telemetry,
process control, data strorage,
communication between processes
For this reason, it is worth considering an introductory overview of SCADA in this
course. When working with DCS in the future, you are likely to come across SCADA
systems too.
1.3.1 Classic SCADA systems (old!)
Sensors
Figure 1.5: Classic SCADA system
The very first SCADA system implemented a Sensor to Panel type scheme (see Figure
1.5). It simply consisted of:
➢ (1) an array of sensors
➢ (2) control panel of meters
➢ (3) lights and recorders
An operator would then be in charge of various control knobs which would exercise
supervisory control. A Sensor to Panel type SCADA system has the following
advantages and disadvantages
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Advantages:
➢ It is a simple system – no CPU, memory, or software programming.
➢ Sensors are directly connected to meters, lights etc.
➢ Cheap and easy to add extra switches and indicators.
Disadvantages:
➢ As the system expands, the amount of wiring becomes unmanageable.
➢ Re-configuring system is very difficult.
➢ The amount of data that can be retrieved is very limited.
➢ Storage of data is minimal.
➢ No off site monitoring of data or alarms.
➢ Somebody has to watch the control panel 24 hours a day.
Whilst these systems are relatively unsophisticated, they can still be seen in practice
today in manufacturing plants, factories, and power generating facilities.
Nowadays, SCADA systems are much more advanced. A modern SCADA system is
the combination of telemetry systems and the control of the data acquisition. In modern
industrial and manufacturing plants, telemetry is often needed to connect equipment
which may be separated by large distances (- this could potentially be anything up to
several thousand kilometres). It is the function of the telemetry systems to send
commands, and receive monitoring signals, from these remote systems.
A typical modern SCADA system now has five levels of hierarchy (Figure 1.6):
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1.3.2 Modern SCADA systems (state of the art!)
Modem
Wireless
Modem
Internet
Gateway
Modem
Telephone
Landline
Wireless
Modem
Wireless
Modem
Local Area Network
Sensors,
measurement
devices
Sensors,
measurement
devices
Sensors,
measurement
devices
Sensors,
measurement
devices
Operator Stations
Mainframe Computer,
Data Processing System
Figure 1.6: Typical modern SCADA system
Commercial
Data Processing
System
Master Station
Communication
System
Remote
Terminal
Units
Field Level
Instrumentation
and Devices
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Field Level Instrumentation and Control Devices
➢ Sensors and Process Control Equipment are used for obtaining measurements
and data from the environment.
For example, temperature readings in chemical processes, the position of components
etc.
Remote Terminal Units
➢ These are essentially industrial PC based systems which are responsible for
collecting field information and data.
A SCADA system usually consists of several Remote Terminal Units.
Communication System
➢ A communication system is required to link the RTUs to the Master Unit. The
communication medium depends upon the location of the RTUs, and the
technology available.
Master Station
Each RTU is connected to a Master unit which retrieves data.
➢ It is the responsibility of the Master unit to collect all the data acquired from the
RTUs. The Master unit displays data and enables the operator to perform
remote maintenance and control tasks via a Human Machine Interface (HMI).
Often, multiple operator stations will be connected to the Master unit, allowing
different personnel access to the data.
Commercial Data Processing System
➢ In larger telemetry systems, a separate data processing system may be
available to co-ordinate and manage large volumes of data - useful for storing
backup data, and determining long term data trends.
1.3.2.1 System Implementation
When implementing a new SCADA based system, consideration always has to be
given to the cost versus quality of the system. It is important to be aware that nobody
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has an endless budget! Reliability is always an important consideration. However, is
it justifiable to spend, for example, ten times more on a particular type of system, when
it only improves the reliability by 1%??….As with most engineering problems,
compromise might be necessary.
Consideration should also be given to integration with existing technology. In some
cases, this may avoid the cost of setting up new communication infrastructures.
Possible options might be using the existing LAN networks, using the existing
telephone lines, or even radio/wireless systems. In doing this, however, care must be
taken not to compromise the existing communication network. Furthermore, it must
not interfere with other existing facilities.
1.3.2.2 SCADA Software
The detail of SCADA software systems is outside the scope of this course. However,
a general appreciation of the core functions of the software is worth noting. The key
components of any SCADA software platform are:
➢ Graphical User Interface
➢ Alarms
➢ Trends
➢ RTU Interface
➢ Scalability
➢ Database
➢ Networking
➢ Fault tolerance and redundancy
➢ Distributed Processing
SCADA software can typically come in two forms; proprietary or open.
➢ Proprietary software is written by individual companies to work with their own
hardware. These systems are typically sold as a complete hardware and
software solution.
➢ Open software is typically written by independent companies, and they target
their software to work with a number of different manufacturers hardware
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1.3.3 Remote Terminal Unit Hardware
As mentioned previously, Remote Terminal Units (RTUs) are essentially industrial PC
based systems which are responsible for collecting field information and data. Typical
RTU hardware modules consist of several components, as shown in Figure 1.7.
Power
Supply
Central
Processing
Unit
Analog
Input
Module
Analog
Output
Module
Digital
Output
Module
Digital
Input
Module
CENTRAL BUS
Memory
240V
AC
Communication Ports
RS232/RS422/RS485
Figure 1.7: Typical RTU unit
1.3.3.1 Power Supply
➢ Typically converts 240V ac supply input into low voltage DC output, for
powering the digital and analogue hardware in the RTU; typically 5Vdc and
12Vdc. In some cases, industrial equipment will operate on 24V and 48V
technology
1.3.3.2 Central Processing Unit
➢ The central processing unit is usually a 16bit or 32bit microprocessor based
system. The processor unit will usually contain a modest amount of memory
internal to the chip.
➢ The processor is usually driven by a real time clock, which may include a
calendar feature to enable time stamping of events.
1.3.3.3 Memory
➢ When more memory is needed, external memory is usually used which
interfaces to the processor. This can be in the form EPROM, RAM, or Flash
Memory.
➢ It is common to see systems with a combination of these memory technologies.
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(1) Erasable Programmable Read-Only Memory (EPROM),
An EPROM is a memory chip that retains its data when the power supply is
switched off. We refer to this type of memory as non-volatile. Once
programmed, an EPROM can only be erased by exposing it to ultraviolet light.
(2) Random-access memory (RAM):
RAM is typically used for computer data storage. It is necessary for running
computer programs. It allows stored data to be accessed in any order, i.e. at
random, hence the name. RAM does NOT retain its data when the power
supply is switched off. We refer to this type of memory as volatile.
(3) Flash memory
Flash memory is non-volatile computer memory - it retains its data when the
power supply is switched off. It is used for transferring data between devices
and can be primarily found in USB flash drives and memory cards (e.g.
Compact Flash, SD etc)
1.3.3.4 Analogue Inputs
Figure 1.8 shows a typical analogue input module. There are five components worth
mentioning.
Sample
and Hold
Sample
and Hold
Sample
and Hold
Sample
and Hold
Channel
Select
ADC Multiplexer
Bus
InterfaceB
u
s
C
o
n
n
e
c
to
r
TimingClock
Amplifier
E
n
d
o
f
C
o
n
v
e
rs
io
n
S
ta
rt
o
f
C
o
n
v
e
rs
io
n
Sample Inputs
B
u
s
C
o
n
n
e
c
to
r
B
u
s
E
b
a
b
le
Figure 1.8: Example of an Analogue Input circuit
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(1) Analogue to Digital Converter (ADC)
The Analogue to Digital Converter device is at the heart of this module. Its purpose
is to measure an analogue input voltage and convert it to a digital output.
➢ It is important to choose a device which is capable of meeting the demands of
your application. There are several methods of converting an analogue signal
to a digital signal. You may wish to research the following types of device in
your own time:
Successive approximation ADC
Integrating ADC (sometimes referred to as dual slope ADC)
➢ The speed and resolution of ADC converter devices can vary significantly.
There is a trade-off between the two, the faster the ADC, typically the lower the
resolution you can achieve.
(2) Sample and Hold Circuitry
Analogue to digital converters require a fixed amount of time in which to perform
the conversion to a digital signal → the conversion is not instantaneous! For this
reason, a sample and hold circuit is required. A typical sample and hold circuit is
shown in Figure 1.9.
) ( ˆ t u ) ( t u Buffer Hold
Sample
Figure 1.9: Typical “Sample and Hold” Circuit
➢ The sample and hold circuit samples the analogue input and holds the signal
value until the ADC has time to complete the conversion.
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t
V
Figure 1.10: Effect of Sample and Hold circuitry on measured signal
(3) Multiplexer
➢ A multiplexer is a component which sequentially samples many inputs, and
switches the samples to the output in sequence. The output is then passed to
the analogue to digital converter.
➢ Multiplexers are primarily used for cost saving. With a multiplexer, only one
ADC device is required. Without the multiplexer, we would need a separate
ADC for each input channel.
(4) Amplifier
➢ An amplifier may be needed (Note: not always needed!) to match the range of
the analogue signal to the input range of the ADC device. This can be important
if we have very small analogue signals from a sensor. Without the amplifier we
may lose measurement resolution.
(5) Bus Interface and Timing Unit
➢ Once the analogue signal is converted to digital format, the signal is transmitted
to the CPU via the bus. An interface circuit is required to control the flow of data
onto this bus.
➢ The bus interface circuit makes sure that data is only put onto the bus when
needed. This is important to avoid data conflict with other devices sharing the
bus (i.e. bus contention problems).
➢ To facilitate this, a timing unit usually controls the bus interface logic. The timing
unit will also control the acquisition of the input signals and multiplexer.
Measured Signal
Signal after S&H
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1.3.3.5 Analogue Outputs
➢ Analogue outputs perform the opposite function to inputs. They convert digital
signals to analogue signals using a DAC (digital to analogue converter). It is
common to have several analogue output channels. These outputs are typically
used to interface with analogue devices, and perhaps instrumentation such as
oscilloscopes.
1.3.3.6 Digital Inputs and Outputs
➢ Digital Inputs are usually for status and alarm signals.
➢ It is quite common to see digital input boards with 16, 32, or even 64 digital
input channels.
➢ Digital output modules can be used to send simple ON/OFF signals. They are
particularly useful for enabling or disabling devices. You may see LED
indicators for each output to give a quick visual on the status of these lines
1.3.3.7 Communication Interfaces
Typically, an RTU will contain several communication ports.
➢ Typically, an RTU will contain several communication ports. Often, these are
RS232, RS422 or RS485. They are used to interface to operator stations,
diagnostic terminals etc.
➢ Nowadays, Ethernet is commonly included which allows connection to a central
site
1.3.3.8 A rack / enclosure
➢ All the electronics is typically housed in a standardised 19” industrial PC rack
(e.g. VME rack), or a commercial supplied enclosure.
➢ The enclosure is responsible for protecting the components from being
damaged. Not only should the enclosure be strong, it may need to provide
additional protection to prevent moisture, or maybe dust, getting into the
electronics. Finally, in environments which experience a lot of Electromagnetic
interference (EMI), the enclosure may have to provide shielding.
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Figure 1.11: Example Industrial PC Racks
1.4 Microprocessor and System Measurements
1.4.1 Microprocessor
➢ Microprocessors and Digital Signal Processors (DSP) are designed to
carry out computational processes and mathematical algorithms as
quickly as possible.
In this section, we will consider how these processors are designed to perform as
efficiently as possible. To start, we need to distinguish between off-line processing
and real-time processing.
Off-Line Processing
➢ Off-line processing is typical of personal computers. It relies on the entire
input signal being present and available in the computer system at the
same time.
Example: an engineer may use a data logging system to measure the temperature of
an electrical machine over time. After the experiment, the information is downloaded
to a computer to be analysed (e.g. Matlab). The crucial point to note here is that all of
the information is available immediately to the computer program.
Real Time Processing
➢ Real time processing is typical of Digital Signal Processors. Real-time
applications involve sampling an input signal, performing an algorithm,
and outputting a sample….over-and-over again, at as fast a rate as
possible.
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➢ The important point to remember is that not all the information is immediately
available to the processing program. Furthermore, timing and processing speed
is critical.
Example: an engineer might use a microprocessor based RTU to sample the
temperature of a room. The microprocessor will follow an algorithm to ensure the room
temperature is kept at 20oC. To achieve this, an output sample is generated to control
the heating system to maintain the required temperature. Applications like this must
have the information available immediately. (In practice, there may be a short delay,
but this is usually not a problem: For example, a 100 millisecond delay between
acquiring the temperature measurement and engaging the actuator for the heating
system is unlikely to cause a big problem.
1.4.1.1 Typical task execution within a microprocessor
The typical sequence of events for a microprocessor driven system is summarised in
Figure 1.12. The primary aim of the microprocessor is to carry out these steps as fast
as possible.
Detect and Handle
Interrupt
Hardware Interrupt
Execute Algorithm
Move outputs to network/
DAC
Move outputs to the
output buffer
Obtain data via network
or ADC
Figure 1.12: Typical sequence of events within a microprocessor
1.4.1.2 Interrupts
In real-time processing, events and algorithms are usually implemented using
interrupts.
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➢ An interrupt is basically a signal from hardware (internal or external) that tells
the software to perform an operation, or sequence of operations.

➢ When the interrupt signal is sent, we say that an interrupt request (IRQ) has
been established.

➢ This request is then handled by the operating system. The operating system
will then call the Interrupt Service Routine (ISR). This is simply a software
routine which carries out the process algorithm.


time
Device
turn ON
Algorithm
PLC – say 10ms
Drive System – say 100us
Interrupt cycle time
Alg..

Figure 1.13: Typical timeline of events within interrupt cycle

Note: There are two types of interrupts, Edge-Triggered and Level-Triggered. Edge-
Triggered interrupts are interrupts which are caused by changing the bus line level, it
is basically a transition from a 1 to 0 or from 0 to 1 (falling-edge and rising-edge
respectively).

➢ In real time processing applications, it is important that all the processes are
completed within the interrupt cycle time. When the execution of events takes
too long, we refer to this as an overrun.

This requires the engineer to be aware of the time it takes for the software to execute
on the microprocessor. If overruns occur, the engineer may need to optimise the
software or, in severe cases, possibly consider a more powerful microprocessor
platform.


time
Device
turn ON
Algorithm
Interrupt cycle time

Figure 1.14: Interrupt Overrun, algorithm is not completed in available interrupt time
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1.4.1.3 Circular Buffering
Whilst executing the Interrupt Service Routine, microprocessors are continually
sampling external signals in real time. However, in order to calculate an output sample,
we often need access to a series of recent, but previous, samples from the input.

➢ To handle this situation we must store data and update sample data in the
memory map. To manage the data we usually use a technique known as
circular buffering.
This is best explained via an example. Consider Figure 1.15; this shows an eight
sample circular buffer.

8001
8002
8003
8004
8005
8006
8007
8008 x(n)
x(n-7)
x(n-6)
x(n-2)
x(n-1)
x(n-5)
x(n-4)
x(n-3)
newest
sample
oldest
sample
0.2
2.3
2.0
0.8
0.5
1.7
1.4
1.1


Figure 1.15: Circular Buffering

➢ Here, eight samples are stored in memory and continually updated as new
samples are acquired.

➢ We have placed this circular buffer in eight consecutive memory locations within
the defined memory map, 8001 to 8008.

Figure 1.16 shows how the eight samples from the input might be stored at one
particular instant in time, while (b) shows the changes after the next sample is
acquired.

8001
8002
8003
8004
8005
8006
8007
8008
x(n)
x(n-7)
x(n-6)
x(n-2)
x(n-1)
x(n-5)
x(n-4)
x(n-3)
newest
sample
0.2
-0.1
-0.4
0.8
0.5
-0.7
-1.0
-1.3

8001
8002
8003
8004
8005
8006
8007
8008
x(n)
x(n-7)
x(n-6)
x(n-2)
x(n-1)
x(n-5)
x(n-4)
x(n-3)
newest
sample
0.2
-0.1
-0.4
-1.6
0.5
-0.7
-1.0
-1.3

(a) (b)
Figure 1.16: Circular Buffering Example

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➢ The idea of circular buffering is that the end of this linear array is connected to
its beginning; in the example memory location 8001 is viewed as being next to
8008.

➢ You keep track of the array by a pointer (a variable whose value is an address)
that indicates where the most recent sample resides.

For instance, in (a) the pointer contains the address 8005, while in (b) it contains 8006.
When a new sample is acquired, it replaces the oldest sample in the array, and the
pointer is moved one address ahead.

➢ Circular buffers are efficient because only one value needs to be changed
when a new sample is acquired.

Four parameters are needed to manage a circular buffer.

➢ (1) There must be a pointer that indicates the start of the circular buffer in
memory (in this example, 8001).
➢ (2) There must be a pointer indicating the end of the array (e.g., 8008), or a
variable that holds its length (e.g., 8).
➢ (3) Third, the step size of the memory addressing must be specified. (Note: In
our example, the step size is one, e.g: address 8003 contains a single sample,
just like 8004 does, and so on. This is not always the case)
➢ (4) The pointer to the most recent sample must be modified as each new
sample is acquired. This process must be very fast to optimise the speed of the
microprocessor

The first three values define the size and configuration of the circular buffer, and will
not change during the program operation.

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1.4.1.4 SDL Exercise 1: Choosing a DSP Processor
Please read the technical paper on Canvas entitled “Choosing a DSP
Processor”. Then, answer the following questions….
(1) What is the fundamental difference between a fixed point microprocessor,
and a floating point microprocessor?
➢ …………………………………………………………………..………………………
…………………………………………………………..………………………………
…………………………………………………..………………………………………
…………………………………………..………………………………………………
…………………………………..………………………………………………………
…………………………..………………………………………………………………
…………………..………………………………………………………………………
…………..………………………………………………………………………………
…..………………
(2) What are the main advantages and disadvantages of fixed point and floating
point processors?
➢ …………………………………………………………………..………………………
…………………………………………………………..………………………………
…………………………………………………..………………………………………
…………………………………………..………………………………………………
…………………………………..………………………………………………………
…………………………..………………………………………………………………
…………………..………………………………………………………………………
…………..………………………………………………………………………………
…..…………………………………………………………………………………..…
………………………………………………………………………………..…………
……

(3) In many applications, power consumption is a major concern. Describe the
Power Management features which are available on some modern DSPs.
➢ …………………………………………………………………..………………………
…………………………………………………………..………………………………
…………………………………………………..………………………………………
…………………………………………..………………………………………………
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…………………………………..………………………………………………………
…………………………..………………………………………………………………
…………………..………………………………………………………………………
…………..………………………………………………………………………………
…..…………………………………………………………………………………..…
………………………………………………………………………………..…………
………………………………………………………………………..………………

(4) When looking to the performance of different DSP chips, why do we need to
be caution when comparing “execution speed” statistics?

➢ …………………………………………………………………..………………………
…………………………………………………………..………………………………
…………………………………………………..………………………………………
…………………………………………..………………………………………………
…………………………………..………………………………………………………
…………………………..………………………………………………………………
…………………..………………………………………………………………………
…………..………………………………………………………………………………
…..…………………………………………………………………………………..…
………………………………………………………………………………..…………
………………………………………………………………………..………………
(5) When purchasing any microprocessor based system, (such as an RTU), the
cost of the DSP chip is very important. What are the key factors which influence
the price of the DSP?
➢ …………………………………………………………………..………………………
…………………………………………………………..………………………………
…………………………………………………..………………………………………
…………………………………………..………………………………………………
…………………………………..………………………………………………………
…………………………..………………………………………………………………
…………………..………………………………………………………………………
…………..………………………………………………………………………………
…..…………………………………………………………………………………..…
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………………………………………………………………………………..…………
………………………………………………………………………..………………
(6) Fast DSP operation depends heavily on the speed instructions can be
fetched from memory. There are several ways to achieve this. Draw a diagram
to show the difference between the “Harvard Architecture” and the “Von
Neumann” architecture. What is the basic advantage of the Harvard
architecture?
➢ …………………………………………………………………..………………………
…………………………………………………………..………………………………
…………………………………………………..………………………………………
…………………………………………..………………………………………………
…………………………………..………………………………………………………
…………………………..………………………………………………………………
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………..…………………………………………………………………………………
..…………………………………………………………………………………..……
…………

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1.4.2 System Measurements – effect of digitisation
Here, the actual process of measuring process data will be considered. In particular,
the accuracy of the measurement will be taken into account. Figure 1.17 shows a
simplified block diagram of the measurement process.

Micro
processor
ADC Sensor


Figure 1.17: Simplified block diagram of an ADC measurement channel


1.4.2.1 Signal Amplification
Figure 1.18 shows a typical output signal from a given transducer.
t
V

Figure 1.18: Typical transducer output – a time varying analogue signal

➢ Most sensors will produce an analogue voltage output, which is proportional to
the property being measured.
➢ This voltage may be very small, say in the mV range.
➢ Typically, ADC full scale ranges are in the low volts range; e.g. 0 to 5V, 0V to
10V, -10V to +10V.
➢ For this reason, often the voltage output will need to be amplified (or sometimes
attenuated; gain<1) in order to best match the full scale range (FSR) of the
ADC device.

Given the maximum output expected from the sensor (Vmax_sensor), and the full scale
range of the ADC (Vrange_adc), we must determine a sensible gain for the pre-ADC
amplifier to maximise the resolution of the measurement.
sensor
adcrange
amp
V
V
G
max_
_
=
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Example:
Full scale range of ADC = 0V to 10V
Sensor Output = 0V to 20mV 500320
10
=
−
=
e
Gamp
Full scale range of ADC = -15V to 15V
Sensor Output = 0V to 1V 151
15
==ampG
Full scale range of ADC = -10V to 10V
Sensor Output = 0V to 24V 417.024
10
==ampG

Assuming a perfect amplifier, the signal will be amplified by the exact gain specified
(see Figure 1.19). In practice, it is worth noting that there will be small amounts of non-
linearity/distortion error in the amplification process.

t
V

Figure 1.19: Amplification of transducer output to match ADC input

1.4.2.2 Sampling Process
➢ The signal is sampled using a Sample and Hold circuit (S&H).This snap shots
the measurement and holds the value until we are ready to carry out the
conversion process. Unfortunately, this will also introduce error into the channel
measurement. This is shown in Figure 1.20.

t
V

Figure 1.20: Sampling of amplified transducer output.
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1.4.2.3 Analogue to Digital Conversion
The next stage is the analogue to digital conversion process. There are two key factors
to consider here the ADC Resolution and Quantization error.

➢ Digital systems work with a finite number of discrete values. The ADC resolution
(N bits) allows us to calculate the number of discrete values (Q) that can be
distinguished over the full scale range of the ADC.
It is simply:
NQ 2=

Resolution has a large impact on the measurement accuracy. It is all very well using
an RTD to measure temperature with high accuracy, but by using an ADC with low
resolution, you are throwing most of this accuracy away.

Example: ADC resolution = 6 bits 642
6 ==Q


A more useful way to represent resolution is in terms of volts.

12 −
=
N
FSR
v
V
Q
Example:
Full scale range of ADC = 0 to 10Volts
ADC resolution = 6 bits
V
V
Q
N
FSR
v 159.0
12
10
12 6
=
−
=
−
=

In other words, there needs to be a change of at least 0.159V at the input of a 6 bit
ADC, in order for the output result to change. The ADC will not be able to distinguish
the difference between smaller variations in the input signal.

➢ Anything received between discrete voltage levels has to be approximated to
the nearest level available. This rounding up, or down, of the measured value
is referred to as quantisation.

➢ Quantisation is unavoidable, and is present in all ADC measurements.

Figure 1.21 shows an example, where the signal is always rounded up, or down, to a
discrete level.

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Figure 1.21: Quantisation of Sampled Signal

➢ The term quantisation error is sometimes used to quantify the error between
the actual measurement and the approximated digital value.

The quantisation error at the point of sampling is anything between 0 and 0.5Qv.
(Sometimes this is defined as 0.5LSB – which is half the least significant bit)

Figure 1.22 shows the overall effect of the sampling process. As this clearly
demonstrates, the sampled signal is not a perfect representation of the actual signal
being measured. Therefore, when controlling a process, there is always measurement
error introduced by the digitisation of a signal. As an engineer, you must be aware of
this when designing a control system.


t
V

Figure 1.22: Comparison of actual signal being measured and signal used by microprocessor
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1.4.2.4 Minimising the measurement error
To minimise this error, we may:

➢ Increase the resolution of the ADC converter – increase the number of bits (N).
➢ Use a faster sampling rate – we gain a more accurate representation of the real
signal.
However, we also have to bear in mind

➢ Resolution of the microprocessor unit – for example, there is no point
considering an 18 bit ADC, if the microprocessor is 16 bit. The additional two
bits of ADC resolution will simply be lost.
➢ Faster sampling rates → require more advanced microprocessor systems to
operate
➢ Typically, with a faster sampling rate, the Interrupt Service Routine of the
microprocessor will have to operate at a faster rate (i.e. less time to execute
process algorithms) resulting in potential risk of an overrun situation.
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1.4.2.5 SDL Exercise 2: ADC measurement issues.
Consider the following control problem…..

A petrochemical company wishes to control the temperature of a chemical reaction to
maximise the yield of a particular process within a plant. Previous experience shows
it is important to control the temperature to within 1OC. The temperature range of
interest is 200oC to 500oC. To measure the temperature, a Resistive Temperature
Device (RTD) is used. The RTD produces 0.1mV/oC.

On site, there is an existing 16-bit RTU microprocessor system with a single channel
analogue to digital converter (ADC) input module. The resolution of the ADC is 8 bits
and the full range input of the ADC converter is 0 to +10V.

The input of the ADC converter device is coupled to an adjustable gain amplifier, which
may be set to any value by the user.


i) Is the available system suitable for the intended application, or should
you consider buying new hardware?
ii) What is the minimum resolution ADC required to control the chemical
reaction to within 0.1oC? (Assume a 0 to 10V ADC input range.)
iii) The temperature range of interest is changed; 200oC to 2000oC. What
is the minimum resolution ADC required to now control the chemical
reaction to within 0.1oC?
iv) The existing 8 bit ADC module is changed for an alternative 8 bit
module with an input range of only 0V to 3.3V. Will this improve the
accuracy of the measurement? Quantify your answer.
v) What would be the effect of not having a pre-ADC amplifier? Calculate
the accuracy of the measurement channel without an amplifier.

This is a student directed learning exercise. Therefore, please post your solutions on
the “Discussion” page of Canvas. Take time to consider solutions posted by others,
and feel free to add helpful comments and feedback where appropriate

Depending upon the assumptions made at the start of this problem, it is possible that
different solutions may be offered. Provided the assumptions are fully justified, that is
perfectly acceptable.




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Chapter 2
Communication Medium: Networks
2.1 Aims
On completion of this chapter, you should;

➢ Understand the benefits of network systems.
➢ Have an appreciation of the different communication media available for data
transmission (wired systems)
➢ Appreciate that data transmission is not perfect – sources of noise and signal distortion
➢ Gain an overview of network topologies
➢ Have an understanding of Medium Access Control (MAC) methods
➢ Have an appreciation of the different error checking methods available for data
transmission
➢ Understand the different issues that affect a network performance.
➢ Understand the need for Line Driver in data transmission.
➢ Gain an overview of data synchronisation in a communication system


2.2 Networking and its Benefits
The simple concept of a network system is that multiple devices can be connected to,
and communicate with each other, over a single standardised system.

The effect this has on individual devices will depend on the complexity of the system.

➢ Enabling simple devices to communicate via the network system may
significantly increase the complexity and sophistication of the device.

➢ This will involve extra cost, and the extra benefit to the device itself may be
minimal.

➢ However, the capability to integrate with other devices will expand. And the
overall functionality of the system will be improved. This is the great advantage
of using a network system.



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The main areas in which the concept of networks brings benefits are:

1) Ability for control systems to expand over large geographical areas.
2) Easy to add further devices to the system without the need of system redesign.
3) We can share tasks and delegate to other devices connected to the network -
thereby decreasing the processor load.
4) Standardised minimum wiring between devices and low cost of implementation.
5) A sole basic communications standard for engineers to learn and to maintain.
6) Vendor independence - when the standard is widely accepted by industry (i.e.
open protocols.)

2.3 Data Transmission
This section provides a basic discussion of data transmission. In particular, it is
relevant to industrial wired networks.

➢ Most wired networks work on the basis of serial transmission where parallel
data is converted into serial form for transmission over the network. It is then
converted back from its serial form to its parallel representation by the receiving
end.

➢ The receiving end does this by sampling the transmission line at specific time
intervals and converting this into a logical sequence of ‘1’s and ‘0’s.

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The basic concept of this mode of transmission is shown in Figure 2.1

Signal
Level
Parallel to Serial
Conversion
01 0 1
Transmitting
Node Data
Serial to Parallel
Conversion
01 0 1
Receiving
Node Data
Sample Points
1 1 00
Transmission Medium
Figure 2.1: Typical wired data transmission

Transmission lines form the basis of most of today’s industrial networking systems.
Therefore, an awareness of interconnection technology used in transmission lines is
essential when talking about networks for real-time control.



2.4 Interconnection Technology
Most industrial networks are interconnected using normal wire/cable. Some are
interconnected using optical fibres, whilst others use no cable at all. Wireless networks
use either infra-red or radio technologies (not discussed here). Common
interconnection types used in industrial networks include:

Copper wires

➢ Simple two wire open line is the simplest kind of cable. Typically, a max distance
of 50m and baud rate of 19.2 kbits/sec can be achieved. Normally one line is
used as a common connection and the other for data transmission.


Figure 2.2: Typical copper wired data transmission
Capacitive coupling can cause crosstalk and the lines may be susceptible to noise
signals produced by electromagnetic radiation which is generally picked up one
conductor. Some receivers are differentially driven and therefore incorrect signal
reception occurs.


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Twisted wire pair

➢ Much better noise immunity to spurious noise signals. The proximity of the
conductors means that any interference will be picked up by both conductors
reducing the effect on the difference signal. The twisting also reduces crosstalk.
Possible to achieve 1Mbit/sec and 100m distances.


Figure 2.3: Typical twisted pair data transmission

Co-axial cable

➢ The limiting factor of twisted wire pairs is the skin effect. As the transmission
frequency increases, current tends to flow in the outer surface of the conductor
increasing its electrical resistance and therefore increasing attenuation. This
effect is minimised using co-axial cable and typically it can be used for
transmission frequencies up to 10 Mbit/sec over several hundred metres.



Figure 2.4: Typical co-axial data transmission

Optical Fibre

➢ Optical fibre allows transmission over much larger distances at higher bit rates
and with minimal susceptibility to electromagnetic radiation. Typically, 100’s
Mbits/sec over several kilometres is possible.

➢ Transmission speed is governed not only by the properties of the fibre but also
the response speed of the transceivers used to convert light into electrical
signals and vice versa.

➢ This option tends to be more expensive and also the fibre may have limited
bend radii which may limit its use in machines with moving parts.

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Figure 2.5: Typical fibre optic cable data transmission


2.5 Sources of Noise and Signal Distortion
When transmitting data across wired copper networks, the signal is likely to subject to
sources of noise and signal distortion. Here, with consideration to figure 2.6, we will
discuss the likely effect these sources have on the transmitted signal:

➢ Attenuation: Cabling resistance will cause loss in amplitude of the signal.

➢ Limited bandwidth: The bandwidth limitation of the cabling means that some
of the frequency components of the transmitted signal will be attenuated thus
resulting in signal distortion.

➢ Delay distortion: It is impossible to transmit a signal instantaneously.
Therefore, delay distortion is introduced due to cable propagation effects.

➢ Line noise: Noise picked up by the cable will also add to the transmitted signal
and may produce a very noisy end result. If the combined effect is too great,
the receiver can incorrectly sample the signal resulting in incorrect data
transmission.


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Figure 2.6: Sources of noise and signal distortion in typical wired transmission
Transmitted Data
Transmitted Signal
Attenuation
Limited Bandwidth
Delay Distortion
Line Noise
Combined Effect
Sampling Points
Received Error
Bit Error
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2.6 Networking Topologies
There are several networking topologies. Here we will consider some of the most
common ones.

2.6.1 Bus Network
➢ The simplest layout, low-cost and the most common form of topology is the Bus
network. With this network it is easy to add new nodes and extend the bus.
➢ The disadvantage is that if the cable breaks in one location communication may
be lost with several nodes.



Figure 2.7: Bus Network Topology

2.6.2 Ring Network
➢ Ring topology is common in industrial networks. This type of topology may have
increased cabling and connector costs, but if a cable breaks, this may not
necessarily cause loss of communication.


Figure 2.8: Ring Network Topology
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2.6.3 Star Network
➢ Star topologies are used primarily for telephone systems and wide area
networks. Data are routed through different network paths by *packet switching
devices. Switching components can add to overall costs and may also slow
data rates.

PSPS
PS


Figure 2.9: Star Network Topology

* Packet switching is a network communications method that splits data into smaller
pieces (i.e packets). These are then routed over a shared network. At the receiving
end, the original data is reassembled in the correct order.

2.6.4 Hub Network
This type of network is used for longer distance communication. The Hub network is
similar in geographical layout to a Star network. However, a Hub performs no data or
packet switching (Figure 2.10).

➢ A Hub simply relays frames or electrical signals between different parts of the
network. This type of network has an increased cost and decreased data rates
due to the use of Hubs.

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Hub Hub
Hub
Hub


Figure 2.10: Hub/Tree network


2.6.5 Bus Repeaters
To extend the length of a bus, repeaters are sometimes used. An example of a Bus
network with a repeater is shown in Figure 2.11.



Repeater


Figure 2.11: Bus network using repeaters


➢ A repeater receives a signal and retransmits it at a higher level/higher power so
that the signal can be transmitted over longer distances without degradation.

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2.7 Frame Concept
When transmitting information on a network as a serial bit stream, data are
encapsulated into a frame.

➢ A frame contains several pieces of information that the receiver can use to
decode and check the validity of the contents of the frame and the enclosed
data.

A typical frame consists of a Start of Frame (SOF) field, a Control Field (CF), a Data
Field (DF), an Error Checking Field (ECF) and an End of Frame (EOF) field. This
general frame format is shown in Figure 2.12.


Start of Frame
(SOF)
Error Check Field
(ECF)
Control Field
(CF)
Data Field
(DF)
Signal
Level
End of Frame
(EOF)

Figure 2.12: General frame format



Start of Frame field (SOF)

Contains information, in the form of a bit pattern, denoting to receivers that it is the
start of the transmission. This may include bit patterns for synchronisation of the
receiver clock or for governing access to the bus.


Control Field (CF)

The control field contains information regarding the length of the data and the type of
data included in the frame.

Data Field (DF)

DF - contains any information included in the frame. Different networks will have
different maximum data lengths in each frame.

Error Checking Field (ECF)

ECF - contains information that allows the receiver to check the validity of the data
and/or control fields.

End of Frame (EOF) field

Contains, in general, a fixed format bit pattern denoting to receivers and prospective
transmitters of information that the frame is at an end.
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Example 1: General Data format
Start of Frame
(SOF)
Error Check Field
(ECF)
Control Field
(CF)
Data Field
(DF)
End of Frame
(EOF)
Signal
Level
1100110001110101000101000111011100001111

Figure 2.13: General frame format


Example 2: RS232 Format
Note that a frame may not have all of these fields present. One of the simplest frames
is that used by RS232. The format of an RS232 frame is shown in Figure 2.14.



7 or 8 Data Bits
Start Bit
Parity Bit
1 or 2 Stop Bits
Figure 2.14: RS232 frame format


The start bit represents the SOF and is used by a receiver to resynchronise its clock
so that sampling of subsequent bits is achieved successfully. There is no control field
as the format of the frame is agreed in advance i.e., both transmitter and receiver will
always use the same frame format. The data field consists of seven or eight bits of
data. The parity bit (which may not necessarily be present) represents the error check
field and the stop bits are at the end of the frame.
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2.8 Medium Access Control
In large networks there are many different paths for communication and if two or more
nodes wish to transmit at the same time they can use different network paths, thus
avoiding collisions.

➢ In a Bus or Ring topology all nodes share the same transmission media and therefore
they use Medium Access Control (MAC) methods to prevent data collision.

➢ MAC is used to arbitrate which transmitter in a network gains access to the transmission
media.
➢ It is used to prevent two or more nodes from trying to transmit information at the same
time and thus prevents electrical signals from interfering with one another and causing
data loss or corruption.

Note: There are many different methods for MAC, some of which are described in
standards. e.g., CSMA/CD = IEEE 802.3. Token Bus = IEEE 802.4. Token Ring =
IEEE 802.5.



2.8.1 Poll/Select
Node A Node B
Node C
Master
Request
Response


Figure 2.15: Poll/Select communication

The Poll/Select method is shown in Figure 2.15.

➢ In a Poll/Select mechanism only one station on the network (the master) is
allowed to initiate transmissions.
➢ The master polls devices for information and will only request information from
a device once its previous request has been successfully completed.

➢ An error detection mechanism is inherent within this method of communication:
a node failing to reply to a request after a certain predefined time-out period
may have failed.

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➢ This type of communication can be made quite fast for small networks, although
the loading on the master and the response times and data update rates
increase as the number of nodes on the bus grows.

2.8.2 Carrier Sense Multiple Access with Collision Detection (CSMA/CD)
The Carrier Sense Multiple Access network with Collision Detection CSMA/CD MAC
method is illustrated in Figure 2.16.

Node A Node B
Network
Node A starts transmitting
Node A Node B
Network
Node B starts transmitting the same
time, or nearly the same time


Node A Node B
Network
Nodes detect collision

Node A Node B
Network
Nodes stop transmitting


Figure 2.16: CSMA/CD illustration


➢ In a CSMA/CD MAC network, transmitting nodes first check the network to see
if the bus is clear i.e. there are no electrical signals on the bus (Carrier Sense).

➢ If the bus is idle, a node begins transmission of its frame or message. Other
nodes will see this transmission and will not transmit themselves.

➢ The transmitting node also ‘listens’ to the bus at the same time. Therefore, if
two nodes do try to transmit data simultaneously (or close to it, remember
propagation delays may have an effect) the actual signal on the bus and the
transmitted one (intended signal) will differ.

➢ Both transmitting nodes will detect this variation (Collision Detection) and stop
their transmission.

➢ After a certain period, the nodes will try to re-transmit again provided the bus is
free. This period is sometimes randomly defined, as in the case of Ethernet.

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Application example: In Ethernet when a collision occurs nodes wait for a random
time period before attempting re-transmission. During this time another node may
have started to transmit data. Therefore, the original nodes detecting this situation will
have to wait until the bus is free again. If there are a large number of nodes transmitting
data, the node may face unacceptable delays before being able to transmit its
message. In this type of system problems may occur when message length is long
and there are a large number of nodes trying to transmit information. (e.g. CAN and
Internet)

2.8.3 Token Ring and Token Bus MAC
➢ A control token is a special kind of frame used to arbitrate bus access. In this
scheme the control token is passed from one node to the next and only when
a node has possession of the token may it transmit data.
Node A Node B
Node C
Token


Node A transmitting

Node A Node B
Node C


Node B transmitting

Node A Node B
Node C

Node C passing the token as it has no data to transmit

Figure 2.17: Token Ring MAC transmission
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Consider the system shown in Figure 2.17.

➢ On network initialisation node A has the token and may transmit data.

➢ When node A has finished transmitting data it passes the token to node B which
can then start transmitting.

➢ When node B has finished it passes the token to node C. If node C has no data
to send it immediately passes the token to node A.

There are two variants of this token passing arrangement -Token Bus and Token Ring.
They effectively work in exactly the same way, except that they each operate on a
different network topology: in a Token Ring network the token passing is in a logical
ring, in a Token Bus network the token passing is along a logical line.


In a real time control environment, small amounts of data need to be transmitted at
regular intervals.

➢ To prevent a node from continually transmitting data and monopolising the
token each node is configured to hold the token for a limited period of time,
known as the Token Hold Time (THT).
➢ Care must be taken to make the THT small enough to give the network fast
response times but large enough to allow the node to transmit its data within its
allotted THT: otherwise, a data build up can occur on the node. (Example:
Profibus.)

2.8.4 Slotted Ring
Slotted Ring MAC is primarily used in small Ring networks.

➢ A Slotted Ring MAC network is initialised with a fixed number of bits for
transmission by a special node known as the monitor.

➢ The bit stream is continually shifted around the ring from one node to another.
The ring contains a fixed number of transmission slots each made up of a single
fixed frame of information.









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Start of Field
(SOF)
Slot Empty/
Full
Source
Address
Data
Acknowledge
Field
Destination
Address


Node A Node B
Node C
Monitor


Figure 2.18: Slotted Ring MAC topology

Consider Figure 2.18:

➢ Initially all slots are marked as empty.

➢ When a node detects an empty slot, it fills in the frame with data and the
destination address for the data. It then marks the slot as full.

➢ The slot is then circulated through each node until the destination address
matches the address of the node.

➢ If the addresses do not match, the node simply ignores the slot. If the addresses
match, the node reads the data and sets the acknowledgement field.

➢ The slot re-circulates until it reaches the source (original transmitting node)
which detects the acknowledgement and marks the slot as empty.

➢ If there is no acknowledgement an error has occurred.



➢ Disadvantages are that this type of bus requires a monitor node and the frame
length is fixed, requiring multiple slots for large amounts of data. The time taken
to transmit data increases with the number of nodes in the ring.





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2.9 Error Checking Mechanisms
Several error-checking mechanisms are commonly used to allow a receiver to detect
whether the information has been received correctly. These include:

➢ FORM or FRAME errors where the received frame does not follow the correct
format, BIT errors, for example with the violation of bit encoding rules, and
others. However, these do not check the validity of the data content of the
frame.

➢ Therefore, certain error checking mechanisms are used whereby both
transmitter and receiver perform calculations based on the frame contents.

The result of the calculation by the transmitter is compared to an independent
calculation done by the receiver. If a mismatch exists, then an error has occurred.
Once a receiver detects an error, it will be signalled to the transmitter in several
different ways, for example:

By means of a negative acknowledgement - the receiver replies to a transmitted
message indicating the error has occurred. This mechanism is mostly used in Peer-
to-Peer and Poll/Select networks.

Transmitting an error frame - when a receiver detects an error it transmits an error
frame (e.g. in Controller Area Network (CAN) the error frame consists of 6 Dominant
bits)

Some of the most common error-checking mechanisms will be briefly explained in the
section.

2.9.1 Checksum
➢ The simplest form of error check is the checksum. In a checksum, consecutive
bytes in the frame are added together to form the checksum value.



Note, the checksum may be done on the whole frame or just the data section of the
frame. An example of a checksum calculation is shown below.

0 0 1 0 0 10 0 0 1 0 0 0 10 0


Data Frame Checksum

34:66


100


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Example 1: Determine the checksum for the following transmitted data.

1 1 1 1 1 10 0 0 0 1 1 0 01 0


Data Frame Checksum

238:56

294


Example 2: Determine the checksum for the following transmitted and received data.
Assuming that the received data was originally sent by the transmitter, what can you
conclude about the checksum algorithm?

0 0 1 0 1 11 0 0 0 1 1 0 01 0
0 0 1 0 1 11 1 0 0 1 0 1 11 1
Transmitted Data
Received Data



Data Frame Checksum

Transmitted

54:56


110

Received

55:55


110



Conclusions:

➢ Here, both checksums are correct, but the received data is clearly erroneous.
➢ This method does not detect all errors (in fact, it will fail to detect quite a large
enough proportion of them)

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2.9.2 Parity Check
➢ Parity checking is commonly used in systems. It works by transmitting an extra
parity bit with each byte of data.

For example, the frame format of an RS232 is shown in Figure 2.19.

B0 B1 B2 B3 B4 B5 B6 B7
S
ta
rt
B
it
P
a
ri
ty
S
to
p
B
it
1
S
to
p
B
it
2
Data Bits

Figure 2.19: RS232 frame format

➢ The parity bit is calculated by performing successive XOR operations of the serially
received bits.


The mechanism is illustrated in Figure 2.20.


B0 B1 B2 B3 B4 B5 B6 B7
+
+
+
+
+
+
+
Parity Bit (Even)Parity Bit (Odd)
+ =XOR
P0
P1
P2
P3
P4
P5
P6

Figure 2.20: Illustration of parity check mechanism
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Example 1: Determine the Even and Odd Parity for the following data byte:
1 0 1 1 0 01 1

B0 B1 B2 B3 B4 B5 B6 B7 Operation
1 0 1 1 1 0 0 1
P0 = 1 B0  B1 = 1  0 = 1
P1 = 0 P0  B2 = 1  1 = 0
P2 = 1 P1  B3 = 0  1 = 1
P3 = 0 P2  B4 = 1  1 = 0
P4 = 0 P3  B5 = 0  0 = 0
P5 = 0 P4  B6 = 0  0 = 0
P6 = 1 P5  B7 = 0  1 = 1

Parity (Even) = 1 Parity (Odd) = 0

Example 2: Determine the Even and Odd Parity for the following two bytes of data:
1 0 1 0 0 10 0

B0 B1 B2 B3 B4 B5 B6 B7 Operation

P0 =
P1 =
P2 =
P3 =
P4 =
P5 =
P6 =

Parity (Even) = ………. Parity (Odd) = ……….

0 0 1 1 1 10 0

B0 B1 B2 B3 B4 B5 B6 B7 Operation

P0 =
P1 =
P2 =
P3 =
P4 =
P5 =
P6 =

Parity (Even) = ………. Parity (Odd) = ……….

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Conclusions:

This scheme is useful in detecting single bit errors that may occur between the
transmitter and receiver i.e., if one bit is in error it will be detected.
However, if there are two or more bit errors, the same parity bit may result, in which
case the error will go undetected.





Therefore, the parity bit scheme used in RS232 is said to have a Hamming Distance
of 2 i.e. two binary words may share the same parity value as long as they differ in
more than 1 bit value. An example is shown in the table below.

Data Parity (Even) Parity (Odd)
0000 0000 0 1
0000 0001 1 0
0000 0010 1 0
0000 0011 0 1

2.9.3 Block Parity Check
A variant of the parity bit check is the block parity bit check. In this case successive
data bytes are not only parity checked across each row but corresponding bits in
successive data bytes are also checked. This principle is shown in the table below.

Data

Row Parity
(Even)
Row Parity
(Odd)
0 0 0 0 0 0 1 0 1 0
0 1 0 1 0 0 0 0 0 1
1 0 0 0 0 1 1 0 1 0
0 1 0 0 0 0 0 0 1 0
0 1 0 1 1 1 0 1 1 0
1 0 0 0 0 0 0 0 1 0
1 1 0 0 0 0 1 1 0 1
0 0 0 0 0 1 1 1 1 0
Column parity
(Even)
1 0 0 0 1 1 0 1


Column parity
(Odd)
0 1 1 1 0 0 1 0



Note, this parity bit error checking scheme also permits the detection of two or, in some
cases, more bit errors in the transmission. Additionally, if no more than one bit error
occurs during the transmission, it is possible to locate the erroneous bit and therefore
correct it.

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Data

Row Parity
(Even)
Row Parity
(Odd)
0 0 0 0 0 0 1 0 1 0
0 1 0 1 0 0 0 0 0 1
1 0 0 0 0 1 1 0 1 0
0 1 0 0 0 0 0 0 1 0
0 1 0 1 1 0 0 1 1 0
1 0 0 0 0 0 0 0 1 0
1 1 0 0 0 0 1 1 0 1
0 0 0 0 0 1 1 1 1 0
Column parity
(Even)
1 0 0 0 1 1 0 1


Column parity
(Odd)
0 1 1 1 0 0 1 0



2.9.4 Cyclic Redundancy Check (CRC)
➢ Based on polynomial codes generated through the division of the frame
contents by a generator polynomial. It is also called the frame check
sequence (FCS).

➢ The result of the division is transmitted with the frame. The same operation is
carried out at the receiver end and the results are compared. If the result of the
comparison is zero, then no error has occurred; otherwise, the frame is
erroneous.
The mechanism is carried out as follows:

Let:
M(x) be a frame of length ‘k’ bits. This is the data we wish to transmit.
G(x) be an (n+1) bit number. This is known as the generator polynomial.
R(x) be an ‘n’ bit number such than k>n. This is the remainder of the division. This is
important – because it is the CRC number!
Q(x) be the quotient of the division

Then, at the transmitter we employ the following equation, to calculate the CRC
number:
)(
)(
)(
)(
2)(
xG
xR
xQ
xG
xM
n
+=

,

As mentioned before, the CRC number is the remainder of the division process, R(x).
The data frame and the CRC are then transmitted across the transmission medium.


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At the receiver, we carry out the following calculation

 
)(
)(:)(
xG
xRxM


If the remainder of this calculation is zero, then the data has been transmitted
correctly. Otherwise, there is an error.

Example:

Let M(x) = 11100110. This is an 8 bit long data frame (k=8).
Let G(x) = 11001. Therefore, the generator polynomial is 5 bits (→n=4).

(Note: The generator polynomial must always remain the same throughout the network.
There is no hard and fast rule for the selection of this polynomial. Some polynomials work
better than others but, in general, CRC checking detects 99.8% of all errors.)

Therefore, R(x) will be a 4 bit number. (CRC)

Transmission

Calculation at the transmitter end:
)(
)(
)(
)(
2)(
xG
xR
xQ
xG
xM
n
+=



Step 1: The transmitter multiplies the data frame by 24.

M(x)  24 = 11100110 0000


This is equivalent to shifting the data by 4 places to the left. Or, it is equivalent to
simply adding n zero bits at the end of the frame.

Step 2: The transmitter divides the shifted data frame by the generator polynomial
using Modulo 2 division:






Q(x)
111001100000 11001
+ R(x)
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1 0 1 1 0 1 1 0

1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0
1 1 0 0 1
0 1 0 1 1
0 0 0 0 0
1 0 1 1 1
1 1 0 0 1
1 1 1 0 0
1 1 0 0 1
0 1 0 1 0
0 0 0 0 0
1 0 1 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 0 1
0 0 1 1 0
0 0 0 0 0
0 1 1 0

Step 3: The remainder, R(x) = 0110. This becomes the CRC.
Step 4: the transmitted result is:


Receiver

Second stage: calculation at the receiver end.

Step 1: The receiver divides the transmitted frame (including CRC) by the generator
polynomial:

 
)(
)(:)(
xG
xRxM

10110110 = Q(x)
11100110011011001
.

Step 2: In this case, the remainder equals zero, R(x) = 0000, indicating a correct
reception. (SDL: Check this for yourself!)

➢ If there is an error in the received data e.g.
10110110 = Q(x)
11100110111111001
.
This will result in R(x) = 1001  0. (SDL: Check this result for yourself!)




1 1 1 0 1 10 0 0 1 1 0
Data CRC
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Exercise: Error Checking Mechanisms

i) Look at the table below. It shows a set of data frames received by a node in
a distributed control system, including the parity check information calculated
at the transmitter. The receiver uses block parity (logic sense: ODD) to check
the validity of this set of data. Determine whether the data has arrived at the
receiver correctly, or not. If you believe there is an error, specify which bits have
been received incorrectly.


Row Parity
Check
Data (1) 1 1 1 1 1 1 1
Data (2) 1 0 0 1 0 0 1
Data (3) 1 1 0 1 0 0 0
Data (4) 0 1 1 1 0 0 1
Data (5) 0 0 0 0 0 0 1
Data (6) 0 1 1 0 1 1 1
Column Parity Check 0 1 0 1 0 1


ii) Determine the transmitter generated CRC, given the following message data
and generator polynomial.

M(x) = 11001001
G(x) = 10001

iii) The following message data and CRC arrives at a receiving node.

M(x) = 11001001
R(x) = 0111

Given the network generator polynomial is G(x) = 10001, has the data been
received correctly?

SDL Challenge: Cyclic Redundancy Checking

This task is not compulsory but is certainly worth trying. If you can successfully
complete it, is will prove that you understand the CRC algorithm very well.

Write a program in Matlab, which will demonstrate the CRC process.
Your program should include the following features:

- Perform the transmission algorithm
- Perform the receiver algorithm
- Demonstrate that transmission errors will be detected by the receiver.

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2.10 Practical Issues in Networking

2.10.1 Network Performance
The performance of a network is a result of the combined effects of several factors
such as:

➢ (1) Number of Nodes - Generally, the more nodes on the network the higher the network
load, as larger amounts of data need to be transmitted between various points on the
network.

➢ (2) Distance - can also affect overall speed due to propagation effects.

➢ (3) Baudrate - the sheer speed at which bits are transmitted on the bus.

The faster the network the less time is required to transmit a frame and as a result more
time is available for other nodes to transmit their data. Therefore the baudrate is often used
as a measure of performance but it is not necessarily an accurate measure due to the way in
which MAC is implemented and the way the messaging works.


➢ (4) Frame Size – generally, the larger the frame size the more time elapses before
another node can transmit its data. This results in slower response times.

Note that latency in a network is the time taken between a node wishing to transmit its data
and actually transmitting it. Therefore, longer frame lengths generally mean higher latency.


➢ (5) MAC Method – time taken for media access control that could be used for
transmission of data e.g., time taken to pass a token.

➢ (6) Error Checking Mechanism – time taken in validating the transmission of data

➢ (7) Network Model – the more frames required to transfer data between two nodes the
slower the data update times due to higher network loading.

➢ (8) Protocol Efficiency - measured as the number of data bits in the frame compared to
the total number of bits in the frame i.e.

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Frame
Data
N
N
Protocol Efficiency =

Unfortunately, if the number of data bits is large compared to the total number of frame
bits the protocol efficiency is high, but the reaction time of the network may be reduced.
This is due to the fact that a node transmitting a large amount of data will take up
network bandwidth and other nodes cannot transmit their data.

Network performance for two types of MAC systems is illustrated in Figure 2.21. The
graphs show the mean time a frame takes to be transferred across the network as a
function of the offered load. The load is expressed as the fraction of the available bit
rate and is referred to as normalised throughput.

The transfer time is defined as the time from generation of the frame to the time it is
successfully received. The graphs were calculated from simulations where each
network had 100 nodes randomly wishing to transmit data on the network.


10
8
6
4
2
0.2 0.4 0.6 0.8 1.0
Transfer Time
CSMA/CD
TOKEN
BUS
512 bits/frame
10Mbits/sec
Normalised Throughput
10
8
6
4
2
0.2 0.4 0.6 0.8 1.0
Normalised Throughput
Transfer Time
CSMA/CD
TOKEN
BUS
12,000 bits/frame
10Mbits/sec

(a) (b)
Figure 2.21: Comparison of CSMA/CD and Token Ring performance

➢ From graph (a), it can be concluded that token bus systems behave less
effectively than CSMA/CD networks when the frame size is small.

This is because, in this instance, the time taken to pass the token round to the node
wishing to transmit is significantly longer than for a CSMA/CD network which can
transmit as soon as the carrier is free.

➢ In the second graph, token bus networks perform much better than CSMA/CD
networks as the longer frame size means that a CSMA/CD network must wait
longer (carrier sense) before trying to transmit a frame.
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In either case, the probability of a collision occurring in a CSMA/CD network increases
as the network load or throughput increases. This reaches a critical state when the
throughput or network loading approaches 70%. At this point a node may be
continually trying to gain access to a network and continually colliding with other nodes
or backing off due to sensing of a carrier.

2.10.2 Line drivers – Common signal Standards
Due to the cost and technical limitations of today’s electronic components, most
networks are linked using cables. A simple end-to-end network is shown in Figure
2.22. The diagram shows two devices connected and communicating over the physical
media.

Processor
Network
Interface
Controller
Transceiver/
Line Driver
Address &
Data Bus
Transmit Receive
Processor
Network
Interface
Controller
Transceiver/
Line Driver
Address &
Data Bus
Transmit Receive
Transmission
Medium
Figure 2.22: A simple end-to-end network structure

➢ Transceivers are used to drive the interconnecting cable between networked
components

➢ Interconnections must be driven at the correct voltage and current levels.


Several common standards exist for data transmission over a network or point-to-point
communications link. All that differs between them is the current and voltage signal
levels, which determine the level for logic ‘0’ and a logic ‘1’. The signal properties differ
with respect to noise and maximum data rates.



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TTL line driver

Figure 2.23 shows a typical end-to-end TTL line driver (voltage driver).


➢ Data rates are restricted to less than 115 Kbit/s. Maximum line length is
normally about 15 metres.


TTL
Levels
TTL
Levels
TTL
Levels
Signal
Ground
Transmit Receive
Transmit Receive
1=+V, 0=-V
+V
-V
TTL
Level
+V
-V
+V
-V
+V
-V

Figure 2.23: A typical TTL driven arrangement


Current line driver

A simple arrangement for current driven signals is illustrated in Figure 2.24.
Transmit
Transmit
Receive
Receive
20mA
20mA Current
Detector
Current
Detector


Figure 2.24: A typical current driven arrangement

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➢ The standard 20mA current loop uses current rather than voltage levels for the
representation of logic levels.

➢ Increases transmission distance – up to 1km. Extremely popular in industry
(particularly in process control arenas). Transmission rates are relatively low
due to limitations in the switching circuits.

➢ Logic ‘1’; close switch. → Current detected at receiver.

➢ Logic ‘0’; open switch. → No current detected at receiver

The noise immunity of the system is much higher than for voltage driven systems.
However, the rejection of common mode noise in the current loop arrangement is
less than that of the voltage driven arrangement.


RS422
+V
-V
+V
-V
+V
-V
+V
-V
Rt
Rt
Line A
Line B
+V
-V
Line A
Line B
1 0 1

Figure 2.25: RS422 line driver arrangement.


➢ In RS422 logic ‘1’ and logic ‘0’ are represented by the polarity of a differential
voltage.

➢ Rt is a terminating resistor used to terminate the lines and reduce unwanted
reflected signals, decreasing signal distortion.


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RS485
Figure 2.26 shows the RS485 arrangement.
+V
-V
+V
-V
+V
-V
+V
-V
Rt
Rt
Line A
Line B
+V
-V
Line A
Line B
1 0 1

Figure 2.26: RS485 line driver arrangement

➢ Variant on the RS422 standard. Difference being that several transmitters and
receivers can share the same pair of wires.

➢ Requires special techniques to ensure that no two transmitters try to send
information at the same time, causing data corruption.

➢ RS485 arrangement has been used as the basic concept for many networking
systems such as Profibus and CAN.


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2.10.3 Data synchronisation
In order for data to be transmitted over a serial bus system, parallel-to-serial and serial-
to-parallel conversions of signal levels take place at the transmitting and receiving
ends, respectively.

➢ The receiver must sample the bus at the correct point in time in order for the
correct signal values to be converted back into their parallel representations.

➢ Incorrect sampling results in corrupted messages.


➢ It is important that the sampling clock at the receiver end is synchronised with
the clock of the transmitter.


Figure 2.27 illustrates this concept.


Sample Points
1 0 10
Sample Points Sample Points
1 0 001 1 00

a b c
Figure 2.27: Sampling: (a) sampling correctly, (b) sample time too long,
(c) sample time too short



➢ Two types of bit sampling exist: asynchronous sampling and synchronous
sampling.










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Asynchronous Sampling
An asynchronous sampling scheme is shown in Figure C.8.

Transmit
Clock
(TxC)
PISO
Parallel
Data In
Serial Data Out
Serial
Clock
(RxC)
SIPO
Serial Data In
Parallel
Data Out

Figure 2.28: Asynchronous sampling and synchronisation

➢ In asynchronous sampling, both transmitter and receiver have their own clocks
running at the same frequency.

➢ Generally, the start of the transmission synchronises the clock at the receiver
end with that of the transmitter and from this point on both clocks run
asynchronously from one another.


Note: RS232 works on this principle. Here transmission rates are governed more by
the accuracy of the timing components than by the quality and propagation properties
of the interconnections. Nowadays this is less of a problem, as components
manufacturing precision and therefore timing accuracy have improved.

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Synchronous Sampling
Synchronisation can be done in a number of ways.

A. Transmit clock signal on separate line
The most obvious is to transmit the clock signal using a separate signal conductor.
However, there are disadvantages to this method.

➢ Cabling will require at least one extra conductor → increased cabling cost.

➢ Cable propagation effects - on reaching the receiving end the clock signal may
have drifted sufficiently to cause incorrect sampling times at the receiver.

➢ Additional driving electronics are required to power the cable carrying the clock
signal→ increased cost.

B. Superimpose data and clock signals
An alternative to this is to superimpose both data and clock signals. An example of
this is given in Figure 2.29.



Figure 2.29: Synchronisation by encoding the clock and data signals



➢ Superimposing clock and data signals, however, can create difficulties in
decoding the incoming pulse train.

This is particularly true in the example of Figure 2.29 where the receiving electronics
must decode three different bus signal levels.




1 0 0 1 1 1 0 1
0
+
-
Clock
Signal
Encoded
Signal
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C. Detect transitions on the bus

➢ An alternative method is to use the transitions that will inevitably occur within
the pulse train itself.

➢ This requires the use of a resynchronisation method whereby the sampling
process at the receiving end is synchronised at periodic intervals during
reception of the pulse train.

For this purpose, a digital phase locked loop (DPLL) may be used, as shown in
Figure 2.30.



Local Clock
PISO
Parallel
Data In
Serial Data Out
DPL
L
SIPO
Serial Data In
Parallel
Data Out
Bit encoder Bit decoder
N Local
Clock

Figure 2.30: Synchronous transmission using DPLL

➢ The bit encoding scheme must ensure that the DPLL has enough bit transitions
in order to re-synchronise sampling.


➢ For example, Bit Stuffing: CAN networks insert a bit of the opposite
polarity after every 5 bits of the same value.









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D. Manchester Encoding Scheme

Another alternative is to use the Manchester encoding scheme (sometimes called
phase encoding scheme). Consider Figure 2.31.


1 bit period 1 bit period
Logical ‘1’ Logical ‘0’
1 1
Figure 2.31: Manchester encoding scheme

➢ The Manchester encoding scheme encodes logical ‘1’s and ‘0’s as signal
transitions.

➢ A transition in signal level is guaranteed even if the transmitter is transmitting a
constant stream of ‘1’s or ‘0’s.


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Chapter 3
Network Protocols: ISO Reference Model
3.1 Aims
On completion of this chapter, you should;

➢ Understand the principle of the 7-layer ISO Reference Model!
➢ Understand that this is the foundation of nearly all DCS Network Protocols (e.g.
CANbus, PROFIbus, etc)

3.2 Standards
The International Organisation for Standardisation (ISO) is a voluntary, non-treaty
organisation, which is responsible for developing engineering recommendations.

Membership in ISO is limited to the principal standards group from each country, for
example:

British Standards Institute.

American National Standards Institute (ANSI)*
(* ANSI has assigned the task of developing local area network standards to the Institute of
Electrical and Electronics Engineers)

Do not be misled into thinking that just because membership is voluntary that the
outputs do not really count. They do! In several countries, its recommendations have
been given the force of law.

3.3 The ISO/OSI Reference Model
The standard model for networking protocols and distributed applications is the
International Standard Organization's Open System Interconnect (ISO/OSI) model. It
defines seven network layers; hence the model is also known as the 7-layer ISO/OSI
Reference Model.

➢ It is a framework to support the development and implementation of open
communication protocols.
➢ This model is used as a reference by most present-day specifications.
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3.3.1 The General Framework of The OSI Reference Model
The 7-layer hierarchical model is shown in Figure 3.1. The model is based on the
assumption that there are two co-operating systems wishing to communicate. Each
system is servicing a particular application process.

Layer 7: Application
Layer 6: Presentation
Layer 5: Session
Layer 4: Transport
Layer 3: Network
Layer 2: Data
Layer 1: Physical
Transmission Medium
Application A Processes Application B Processes
Layer 7: Application
Layer 6: Presentation
Layer 5: Session
Layer 4: Transport
Layer 3: Network
Layer 2: Data
Layer 1: Physical

Figure 3.1: ISO/OSI 7-layer model

7 layer model:

➢ The seven layers, from the highest (layer 7) to lowest (layer 1), are called Application,
Presentation, Session, Transport, Network, Data Link and Physical Layers.

➢ The model is based on the assumption that there are two co-operating systems wishing
to communicate. Each system is servicing a particular application process

These applications link to the communications system by using the services of the
uppermost layer of the Reference Model, the Application Layer.
In turn the Application Layer uses the services of the layer below it, the Presentation
Layer without the need for knowledge of any lower layers.

Data is passed between two remote application processes by methods which are
unknown and largely transparent to the application itself.
Each layer is used by the layer immediately above it, and uses the services of the
layer immediately below it. The functionality of all lower layers is hidden and
completely transparent in their operation.
Each layer within the system, as well as calling the layer immediately below it, is in
effect in communication with the equivalent layer in the other process.
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The corresponding elements (peer entities) are responsible for negotiating levels of
reliability of service and data flow control. The rules governing this are known as “layer
protocol”
3.3.2 Data Transfer
Data is transferred between the two application processes (A and B) by being passed
down the layers of one system, transmitted over the communication medium, and then
passed up the layers of the other system.
Data is transferred between layers in the form of 'data units' (DU). Each layer may add
control information to each data unit. This is used to organise the communication
between the peer entities in the two remote systems (see Figure 3.2)



Layer 7: Application
Layer 6: Presentation
Layer 5:Session
Layer 4: Transport
Layer 3: Network
Layer 2: Data
Layer 1: Physical
Transmission Medium
Application A
Processes
Application B
Processes
Process Data
ASDU
A
PCI
PSDU
P
PCI
SSDU
S
PCI
TSDU
T
PCI
NSDU
ASDU
DL
PCI
Complete Transmitted Frame
N
PCI
CRC
Frame
Assembled For
Transmission
Frame
Disassembled
On Reception
SOF EOF
Layer 7: Application
Layer 6: Presentation
Layer 5:Session
Layer 4: Transport
Layer 3: Network
Layer 2: Data
Layer 1: Physical

Figure 3.2: ISO/OSI message construction:
7-Layer Data Transfer Procedure Summary

In application A:

➢ Each layer passes its data to the level below in the form of a Protocol Data Unit
(PDU).
➢ The next layer adds Protocol Control Information (PCI) to that data unit, which
now becomes known as the Service Data Unit (SDU).
➢ This is then passed down to the next lower layer and becomes the SDU for that
layer. The process repeats all the way down to the Physical Layer.

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In application B:

➢ The data frame is received by application B.
➢ As the frame is passed up the layers, the PCI header is stripped off at its
respective layer.
➢ The information held in the PCI header influences the way an individual layer
responds to the SDUs.
➢ When the data unit is passed on to the application from the Application Layer,
only the user data remains.


Note: the ISO/OSI Reference Model is designed to encompass the most complex
communication links.

Some communication systems may not use all seven layers of the model (unused
layers are often called Null Layers). This may be due to the fact that a particular
communications network operates within very strict and limited parameters, so the
functionality of some of the layers is not required. Or it may be that certain commercial
systems are only defined up to a certain level (counting from the Physical Layer
upwards), leaving it to the users to make their own decisions about the higher level
functionality that they need to implement.


3.4 Details of the 7 Layers
Here, we will consider the function of the 7 layers in the ISO/OSI reference model in
more detail. Figure 3.3 is simply a reminder of the 7 layer model.

Layer 7: Application
Layer 6: Presentation
Layer 5: Session
Layer 4: Transport
Layer 3: Network
Layer 2: Data
Layer 1: Physical
Transmission Medium
Application A Processes Application B Processes
Layer 7: Application
Layer 6: Presentation
Layer 5: Session
Layer 4: Transport
Layer 3: Network
Layer 2: Data
Layer 1: Physical

Figure 3.3: ISO/OSI 7-layer model
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3.4.1 Application Layer
The Application Layer is the layer that user programs and processes access to
communicate over the network. It is usually the only access point available to users.

The Application Layer is responsible for:

➢ Providing complete addresses for 'named' remote application processes.
➢ Control of security. Checking the authenticity and authority of the
communications link end systems.
➢ Error control and recovery.
➢ In general, providing all services required for the support of the application
process e.g., file transfer management.
The Application Layer makes use of services provided by all the lower layers.

3.4.2 Presentation Layer
The Presentation Layer provides much of the device independence that is required of
open systems interconnection.

➢ Its main concern is with the syntax of the data, not its interpretation, which is
the responsibility of the Application Layer.
This may include providing conversions from the remote application data
representation to the local application data representation, i.e. encoding and
decoding from the agreed common transmitted data representation into the
local application's format requirements. (e.g. converting from ASCII by a DEC
characters.)

In order to provide this service, a number of Presentation Layer functions have been
defined:

➢ Syntax transformation; this includes data transformation, formatting and special
transformations such as data compression to reduce message size.
➢ Session establishment and termination requests.
➢ Data transfer.

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3.4.3 Session Layer
The Session Layer is concerned with the transactions that occur between two
communicating processes. It deals with the two communicating machines.

➢ The Session Layer is responsible for setting up associations between users or
application processes, and for the termination of information exchanges.

➢ This may be done by using tokens to enable synchronisation on start-up and
re-establishment of connections after link failures. The Session Layer also co-
ordinates the provision of data flow between the communicating systems.

The exact range of functions that the Session Layer may be called on to provide is
application specific. The requirements of the Presentation Layer will influence exactly
which subset(s) of the Session Layer services are required.

Session Layer functionality often includes:

1. Normal data exchange.
Expedited data exchange, when data are required immediately and are given a higher
priority. Expedited data exchanges may overtake data being transferred using normal
data exchange.
Token management used in systems that pass tokens between each other, where
each system is only allowed access to the network when in possession of the token.
Dialogue control of either two way alternate (half-duplex) or two-way simultaneous
(full-duplex) data exchange.
3.4.4 Transport Layer
A fundamental difference exists between the three upper layers and the three lower
levels of the ISO/OSI Reference Model.

➢ The upper three layers, Session, Presentation and Application Layers, are
responsible for providing high-level data communication functions between
network users.

➢ On the other hand, the lower layers, Physical, Data Link and Network, are
concerned with basic data transmission functions either through a direct link
to another machine, or via a cascaded system of links.

➢ The Transport Layer is responsible for bridging the gap between the layers
that provide data transmission functions and the layers that provide
communication functions.

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The Transport Layer is also responsible for overall end-to-end reliable data flow,
providing a service that is independent of the physical media or networks used. This
will include the ability to segment large data structures (or files) into smaller
transmittable sections. Likewise, the Transport Layer would be involved in the
reconstruction of received data structures.

3.4.5 Network Layer
➢ The Network Layer performs the addressing and routing functions needed
to transport messages between the end systems involved.

➢ This can be a complex task if the messages have to pass through a series of
sub-networks to reach their final destination, where each has its own form of
naming and addressing functions.

Where several different sub-networks, using different media-access methods and
data-handling capabilities, are connected, the connections are formed by a device
known as a 'router'. A router operates using the conventions of the lower three levels
of the ISO/OSI Reference Model. It acts as a kind of sorting office to redirect messages
that pass through sets of heterogeneous sub-networks. It identifies the destination of
a message, and can recognise which of the sub-networks to relay the message to so
that the message can reach its final destination.

3.4.6 Data Link Layer
No matter what physical data transmission medium is used, random errors will
occasionally appear during the process of data transmission.

➢ The main purpose of the Data Link Layer is to deal with transmission errors
and thus minimise the number of errors passed on to the higher layers.

➢ This is achieved by constructing the data into a recognisable 'data frame'
structure. The content of the data frame is then analysed before transmission.
Error detection information is added to the data so that errors can be detected
and eventually corrected on the receiver end.

A very common error detection mechanism is the Cyclic Redundancy Check, whereby
the transmitter includes a code in the frame, which is calculated based on the contents
of the data. The receiver then performs its own calculation to obtain an equivalent
code based on the data it received. If the two codes do not match, then an error has
occurred in the transmission.


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Additionally, the Data Link Layer deals with three other main areas of communication.
These are:

1. Flow Control - this is used to cope with the problems inherent with a fast sender
sending messages to a slow receiver. Some method must be employed to slow
down a fast sender while the slow receiver handles previously transferred
messages.

2. Link Management - this deals with the rules that a sender and receiver must
follow in order to exchange information. For example, a sender and receiver
may need to identify themselves to each other and be willing and ready to
communicate before exchanging any data.

3. Medium Access Control - this controls access to the transmission medium itself.

Its purpose is to cope with the problem of two or more stations sending data at the same
time: either by preventing the problem from happening, or by recognising a 'data
collision' (two stations trying to send messages on the transmission medium at the same
time) and resolving the problem so that data and messages are not lost.





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3.4.7 The Physical Layer
The Physical Layer is concerned with transforming or encoding the data passed to it
into some form of signal that can be passed over the transmission medium. The form
the data will take will depend on the transmission medium used (e.g., coaxial cable,
fibre optic cable, or a wireless/broadband system).

Functions of the Physical Layer include:

1. Translating the data into some form of transmittable signal and translating
incoming messages back into usable data.

2. Generating control signals for proper operation of the Data Link Layer - e.g.
collision and bad signal detection. Note that the Physical Layer detects and
signals these events, but it is the Data Link Layer that makes decisions and
takes actions on the signals.

Defining physical connections to the medium - e.g., plug types and pin connections.

Although the Physical Layer describes the connection type to the transmission
medium, it does not dictate the actual form of the transmission medium, nor its
specific performance characteristics. Over long distance connections, signals
may deteriorate to a state that they can no longer be accurately read by the
receiving station. Repeaters can be installed to cope with this problem.
Repeaters are effectively signal boosters; all incoming signals are simply
passed on, but with signal strength restored to acceptable levels. The most
obvious application is in very long distance systems, such as the trans-Atlantic
phone system.









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Chapter 4
CAN: Controller Area Network
4.1 Aims
On completion of this chapter, you should;

➢ Know some of the history of the development of CAN.
➢ Understand CAN technology.
➢ Understand how CAN is related to the ISO/OSI Reference Model.
➢ Identify and understand the Frame format used in CAN.
➢ Understand the MAC system used in CAN.
➢ Know the general organisation of a CAN controller.
➢ Differentiate Basic and Full CAN technology.
➢ Understand CAN message filtering.
➢ Understand CAN error handling.
➢ Identify stand alone and embedded CAN technology.
➢ Identify the differences between CAN protocol and CANOpen protocol.


4.2 Introduction
➢ CAN is a serial bus system especially suited to networking several intelligent devices,
such as sensors and actuators, within a machine or automation cell.

➢ It is a serial bus system with multiple master capabilities. i.e., several CAN nodes can
try to transmit data at any one time.

➢ Each message carries an identifier that establishes a priority system. The node with the
highest priority will be given access to the fieldbus, whilst the lower priority nodes will
wait until the bus is clear

➢ The CAN bus does not need addressing of nodes in the conventional manner. Instead,
messages are sent to all nodes. Each node then decides, based on the message identifier,
whether it is intended for that node or not.

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4.3 CAN Specifications
CAN was originally developed in the 1980s by Robert Bosch GmbH. Its aim was to
overcome communication problems between control systems in cars. One of its first
applications was in Anti-Lock Braking Systems (ABS) and Acceleration Skid Controls
(ASC).

Since then, CAN systems have migrated into many other applications - agricultural
machinery, medical instrumentation, elevator controls, fairground rides and industrial
automation control components.
➢ The original CAN specification developed by Bosch is now called CAN
Specification 2.0 – Part A. This is because an upgraded version of the
specification was released, which contained CAN Specification 2.0 – Part A,
and a new version now called CAN Specification 2.0 – Part B.

➢ CAN Specification 2.0 - Part B, is upward compatible with CAN Specification
2.0 - PART A. The main difference between the two versions lies in the fact that
Part A defines a CAN message with an 11-bit identifier field, while Part B allows
the use of an extended 29-bit identifier.

➢ In 1993, CAN became an ISO standard: reference ISO11898. This Draft
International standard is based on CAN Specification 2.0, but adopts the classic
11-bit identifier format. Today, ISO11898 CAN definition is used throughout the
CAN world

It is worth noting that an alternative CAN standard exists; reference ISO11252. This
specification was developed solely for small applications with much lower
communication speeds. The requirements for implementing a system based upon
ISO11252 are less demanding, hence making it a cheaper solution. In practice, the
number of applications using this standard are much, much fewer than those
applications using ISO11898


4.4 CAN ISO/OSI Reference Model.
➢ In terms of the 7 layer ISO/OSI Reference Model, the functionality of CAN
Specification 2.0 can be interpreted as a two layer protocol.

This is shown in Figure 4.1. Here, it can be seen that CAN operates on the Data Link
Layer and the Physical Layer.
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Application Layer 7
Presentation Layer 6
Session Layer 5
Transport Layer 4
Network Layer 3
Data Layer 2
Physical Layer 1
ISO/OSI Reference Model
CAN Data Link Layer
(CAN specification 2.0)
CAN Physical Layer
(ISO11898)
CAN Protocol
Application Layer
(CANopen)

Figure 4.1: CAN protocol and the ISO/OSI Reference Model

4.5 CAN Physical Layer
➢ The physical medium typically used to implement CAN networks is a
differentially driven two wire bus line with a common return.
➢ The differentially driven wires are called CAN_H and CAN_L, according to the
polarity of the differential voltage between them.

➢ The CAN bus must also be terminated at both ends by resistors with a
recommended value of 124






CAN
NODE A
CAN
NODE C
CAN
NODE B
CAN_L
CAN_H 124
ohms
124
ohms

Figure 4.2: Block diagram of a CAN network

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➢ The maximum length of the CAN bus depends on the baudrate at which it will
be used

CANopen specifies a set of recommended (maximum) baudrate that may be
implemented for a given bus length. This is summarised in the table below (no need to
revise numerical values in this table – for background info only!)
.

Baudrate Bus Length
1Mbit/s 25m
800Kbit/s 50m
500Kbit/s 100m
250Kbit/s 250m
125Kbit/s 500m
50Kbit/s 1000m
20Kbit/s 2500m
10Kbit/s 5000m
Table 4.1: Baudrate and bus lengths recommended by CANopen

4.5.1 Non return to zero (NRZ) representation

CAN bus is NRZ (non-return-to-zero)

➢ In this representation, a change in bus voltage only occurs when a change in
logic is observed. In other words, if a string of logic 1’s is transmitted, no change
in bus voltage is observed.
➢ This is different to the Return to Zero (RZ) scheme, where logic 1 is represented
as a pulse lasting half a clock period.
➢ The NRZ technique guarantees maximum efficiency in bit encoding, and
requires less bandwidth than other encoding methods. However, the full details
of this are not required here.

+V
-V
0
1 0 1 1 0 0 1
C
lo
ck
D
a
ta

T
ra
n
sm
is
si
o
n

Figure 4.3a: Non Return to Zero bit pattern

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+V
-V
0
1 0 1 1 0 0 1
C
lo
ck
D
at
a

T
ra
n
sm
is
si
o
n

Figure 4.3b: Return to Zero bit pattern


4.5.2 Bit Stuffing
➢ CAN requires frequent signal transitions on the bus. This is necessary to
maintain synchronisation of the bits relative to the system clock signal.


To ensure this, a bit stuffing mechanism is implemented to force the bus into a
transition.

➢ The bit-stuffing mechanism consists of inserting a stuff-bit after five
consecutive bits of the same polarity (i.e., five ‘1’s or five ‘0’s)

➢ The stuff bit is always of the opposite polarity to force the occurrence of a
transition on the CANbus.

➢ The receiver node removes the stuff-bit before processing the message.

➢ This mechanism is also used for error control.(Note: We will look at the details
of this later on.)





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1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1
+V
-V
0
1


1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1
+V
-V
0
10 1
S
tu
ff B
it
S
tu
ff B
it

Figure 4.4: Bit Stuffing in CAN




Example 1:


1 1 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1
+V
-V
0
1


1 1 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1
+V
-V
0
10 1






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Example 2:





1 1 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0
+V
-V
0
10 0 1



4.5.3 Bit Timing Configuration
To explain the typical process of configuring a CAN controller for communication at a
particular baudrate, it is necessary to understand bit timing - as defined in the CAN
specification. CAN specifies three timing parameters

➢ The Nominal Bit Rate. Basically, this is the number of bits per second that
corresponds to the desired communication baudrate.
• The Nominal Bit Time. This is defined as 1/Nominal Bit Rate.

Note: The bit timing configuration of a CAN implementation is usually defined
by a Nominal Bit Time parameter, rather than Nominal Bit Rate.

➢ The Time Quantum. This is a fixed unit of time derived from the oscillator
(clock) period.
In CAN implementations there will be a programmable pre-scalar ranging from 1 to
32; Minimum Time Quantum to Maximum Time Quantum.

1 1 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1
+V
-V
0
1
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The process of programming a particular baudrate consists of establishing the duration
of the Time Quantum. Then, the Nominal Bit Time is established, based on the chosen
Time Quantum.
4.5.4 Configuring the Nominal Bit Time.
The structure of the Nominal Bit Time parameter is defined in the CAN specification
as a set of time segments


Sample
Point
Nominal Bit Time
SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2

Figure 4.5: Structure of the Nominal Bit Time parameter


• SYNC_SEG is used to synchronise the different clocks on the nodes connected to the
bus and find where the transition from the previous bit to the current bit is expected to
lie.

• PROP_SEG accounts for propagation delays.

• PHASE_SEG1 and PHASE_SEG2 are adjusted by the CAN controller to compensate
for synchronisation errors, within certain limits specified by the programmer.

By programming the length of the time segments, it is possible to establish the desired
Nominal Bit Time Length. Furthermore, the sample point can be placed at different
locations within the bit time.

The way in which the configuration of these parameters is performed will depend on
the CAN controller’s implementation.


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4.5.5 Physical Connection
➢ CAN controller uses a CAN transceiver for connecting to the bus and
complying with ISO11898 standards.

An example of such a transceiver is the 82C250 chip from Philips.

➢ It is possible to connect to the bus directly, or via optical isolation. Optical
isolation avoids being overloaded by other devices and saves the use of
common return wire. It also improves RF interference.

An example of an optocoupler is the HCPL-7710 from Hewlett Packard.



Figure 4.6: Direct connection between the CAN controller and the CAN transceiver



Figure 4.7: Optically isolated connection between CAN controller and transceiver


➢ Some CAN controllers interpret the serial signals TxD and RxD differentially
rather than comparing them to ground.

➢ When this is the case there will be four wires connecting the controller to the
transceiver: Tx0, Tx1, Rx0 and Rx1.





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4.5.6 Standard Connectors
CANopen reommends (according to DS102), the use of a 9-pin D-Sub connector
(DIN41652). This is shown in Figure 4.8.
1 2 3 4 5
6 7 8 9
5 4 3 2 1
9 8 7 6
Male Female
(GND)
CAN_H
CAN_V+
CAN_L
CAN_GND
(CAN_SHLD)

Figure 4.8: Standard 9-pin D-Sub connector
The defined pin assignments for this connector are shown in Table 4.2.

Pin Signal Description
1 Reserved
2 CAN_L CAN_L bus line (dominant low)
3 CAN_GND CAN Ground
4 Reserved
5 (CAN_SHLD) Optional CAN Shield
6 (GND) Optional CAN Ground
7 CAN_H CAN_H bus line (dominant high)
8 Reserved
9 (CAN_V+) Optional CAN external positive supply
(dedicated for supply of transceiver and
optocoupler if galvanic isolation of the bus
nodes applies)
Table 4.2: CAN connector pin assignments

Note: This is a recommendation. Other types of connectors are allowed, ranging from
5-pin Mini Style connectors to multi-pole connectors.

➢ Reserved Pins – often left unused for possible future development of protocol.

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4.6 CAN Bus Basic Operation
The CANbus and nodes connected to it behave as a wired AND circuit.

Consider Figure 4.9:


Figure 4.9: Wired-AND configuration

Here, each transistor represents the connection of a CAN node to the CAN bus.

➢ Each node can transmit a logic ‘1’ by switching the transistor OFF, or a logic ‘0’
by switching the transistor ON
➢ This circuit implements a wired-AND configuration, because all nodes must be
transmitting a logic ‘1’ in order to have a logic ‘1’ on the bus.

➢ In other words, to have a logic ‘0’ on the bus, only one node needs to transmit
a logic 0.

➢ For this reason, a bit value of ‘0’ is called a Dominant bit in the CAN bus
system, and a bit value of ‘1’ is called Recessive.


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4.7 CAN Data Link Layer
Data Link Layer
Physical Layers
LLC
Acceptance Filtering
Overload Notification
Recovery Management
MAC
Data Encapsulation
Decapsulation
Frame Coding
Medium Access Management
Error Detection
Error Signalling
Acknowledgement
Serialisation/Deserialisation
Bit Encoding/Decoding
Bit Timing
Synchronisation
Fault
Confinement
Bus Failure
Management


Figure 4.10: CAN Data Link Layer
➢ The Data Link Layer can be divided into two sub-layers: the Medium Access
Control and the Logical Link Control.

➢ The Medium Access Control* component is responsible for determining
which node in the network is assigned control of the bus for message
transmission (*We have already dealt with the concept of MAC methods in a previous
section)

➢ The Logical Link Control ensures that the higher layers in the network are
provided with an interface that is independent of the underlying layers (the
Physical Layer and the Medium Access Control).

➢ In practice, this means that the Logical Link Control is responsible for the
detection and correction of errors when data are exchanged through the bus
i.e. it must implement an error-safe transmission mechanism.
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4.7.1 Frame Formats
To be able to carry out its tasks, the CAN Data Link Layer assembles the data to be
transmitted into Data Frames.
4.7.1.1 Standard CAN data frame (11 bit identifier)
Consider the example shown in Figure 4.11 This is a standard Data Frame, as defined
in the CAN 2.0-Part B specification for an 11-bit identifier messages.

Figure 4.11: The CAN 2.0-Part B standard data frame
As shown, the CAN Data Frame is composed of a number of fields:

Start Of Frame (SOF) Field

➢ This field is used to indicate the start of the message. It is composed of a single
Dominant bit and is used to synchronise the nodes on the bus after being idle.


Arbitration Field

This field has two components:

• The first component is an 11-bit identifier, which establishes the message's priority
and its identity. The lower the number, the higher the priority.

➢ The second component is the Remote Transmission Request bit (RTR);

o If this bit is set Dominant, it indicates that the frame contains Data.
o If this bit is set Recessive, it indicates that the frame is a Remote Frame.

A Remote Frame is similar to a data frame, except that is contains no message data. It can
be used to request the transmission of a data frame from another node on the bus.


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Control Field
This field has three components:

• The first is the Identifier Extension (IDE); Recessive (29 bits), Dominant (11-bit).
• The second component is a reserved bit (r0). (for possible future use, in the event
of standard amendments)
• The last component is a 4-bit long Data Length Code (DLC). This contains the
number of bytes being transmitted

Data Field

➢ This is the field where data bytes are sent and can hold between 0 and 8 bytes of
data.

Cyclic Redundancy Check (CRC) Field

➢ This field is used for error checking and contains a 15-bit CRC code followed by a
Recessive delimiter bit.

Ack. Field

➢ This is used to ensure that the data has been successfully received by other
node.
➢ The transmitter inserts a Recessive bit into the first position within this field.
Message reception is acknowledged by overwriting the recessive bit in the
first position within this field with a dominant bit. The transmitter then detects
the dominant bit, and knows the message has been received.
➢ The second bit in the Acknowledge field is just a Recessive bit delimiter.

End of Frame Field

➢ This field is composed of seven recessive bits. (Note: bit stuffing is disabled for this
field)

4.7.1.2 Error Frames and Overload frames
In addition to Data Frames and Remote Frames, the CAN protocol specifies to other
frame types; Error Frames and Overload Frames


• Error Frames: composed of six consecutive bits of the same polarity. This is the
usual way for aborting transmission of frames in which errors are detected.


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This is the usual way for aborting transmission of frames in which errors were detected. A node
transmitting an error frame forces all other nodes in the network to send an error frame as well.
The original transmitter will then try to transmit the original message again.


• Overload Frames: are used when a receiver wishes to delay the transmission of Data
Frames or Remote Frames when it is not ready to receive them. It is used when the
system becomes overly busy.

4.7.1.3 Extended CAN data frame (29 bit identifier)


Figure 4.12: The CAN 2.0- Part B extended data frame

➢ The SRR (Substitute Remote Request) is a recessive bit that substitute the RTR bit in
the 11-bit identifier frame. This bit is followed by a recessive IDE bit in the extended
frame format.

➢ The IDE bit is part of the arbitration field in the extended format.

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4.7.2 Message Filtering
➢ When data is to be transmitted onto the bus, no station is addressed in the
conventional manner. Instead, each message is designated by a unique
identifier in the Arbitration Field.

➢ If a node wishes to transmit information, it simply passes the data and the
identifier to its CAN controller and sets the relevant transmit request.

➢ It is then the responsibility of the CAN controller to format the message contents
and transmit the data in the form of a CAN frame.

➢ Once a node has gained access to the bus and transmitted the data, all other
nodes become receivers.

➢ Having received the message, each node then performs an acceptance test
to determine whether the data is relevant to that particular node. This process
is called Message filtering.

This process means that communication is not limited to a peer-to-peer basis – where
a single node transmits, and another receives. Instead, multiple nodes can accept the
same message using a single transmission. This helps reduce bus loading.

➢ In networking, this concept is referred to as the Producer/Consumer model.

A major difference between CAN and other fieldbus solutions is that this mechanism
requires no interaction from a bus master or arbiter: it follows a multi-master concept.


4.7.3 Bus Arbitration
➢ The identifier in a CAN message also defines the priority of the message and is the
basis for the Medium Access Control mechanism
➢ When a device detects that the bus is free, it starts to transmit its message
➢ During the transmission, the device keeps monitoring the bus. In this way, it checks
if the bus is responding to the message
➢ If during transmission, the node attempts to transmit a Recessive bit, but it detects
a Dominant bit on the bus, it will stop transmission and wait for the bus to be free
again before restarting.
This mechanism is the essence of Medium Access Control in CAN. An example of its
operation is shown in figure 4.13

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Node A
Node B
Node C
Bus
SOF
R

D
R

D
R

D
R

D
ID = 1493
ID = 1501
ID = 2013
ID = 1493
Node C loses arbitration Node B loses arbitration

Figure 4.13: Example of the operation of the CAN MAC mechanism

• The Medium Access Control mechanism in CAN is CSMA/CD-NDBA. It ensures a
non-centralised, non-destructive bus allocation (NDBA) method, based on priority and
need, which is ideal for real-time distributed control applications.

Note: This scheme ensures no bandwidth is wasted during the arbitration process.
Ethernet (for example) also uses CSMA/CD but if there is a collision between two
nodes, one node will transmit a jamming signal, causing both nodes to back off the
bus. Hence CAN is deterministic and has predictable behaviour and very efficient
bandwidth use of the bus; 100% bus loading possible.

4.7.4 Error Handling
Data Link Layer is also responsible for the Logical Link Control for a reliable
transmission. This is achieved through the implementation of several error checking
mechanisms. These mechanisms are:

➢ Bit Error - a node that, after transmitting the Arbitration Field, is still in control of the
medium keeps monitoring the bus, checking if it is responding correctly to the
transmission.

➢ Bit Stuffing Error – bit stuffing has been mentioned earlier. When a receiver detects
six consecutive bits of the same polarity, it knows that a bit stuffing error has occurred.

➢ Cyclic Redundancy Check Error – CRC checking has been mentioned earlier. The
transmitter calculates a CRC code based on the contents of the message. At the receiver,
a CRC code is recalculated and compared. If the transmitter and receiver codes are
different a CRC error has occurred.

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➢ Form Error - there is a mechanism built into CAN that verifies the structure of the
transmitted frame by checking bit-fields within it against the fixed frame format and
the fixed frame size.

➢ Acknowledgement Error –mechanism to make sure receiver(s) set Ack. Field with a
Dominant bit. As mentioned earlier, if a recipient does not set the Ack. field, it is clear
that a transmission error has occurred, and no node has received the message accurately.
4.7.4.1 Error Flags
A CAN node detecting an error is able to abort the transmission by sending an Error
Flag to the other nodes in the network. The type of error flag (Active or Passive)
depends on the error status of the device.

• Error Active - the device is completely sure that an error has occurred and that this
error was not its own fault. Active Error Flag is composed of six Dominant bits.


• Error Passive - when the device detects an error, it suspects that the source of that
error might be local. Since Passive Error Flags are composed of six Recessive bits,
the transmission is generally only aborted if the device is the transmitter of the message
or if it is the only receiver.

• Bus-off - the device believes that it is the cause for the error i.e., it is not capable of
communicating correctly. The erroneous node therefore ceases to participate in the
communication so as not to disturb other nodes on the bus.


To determine in which error state the node is, CAN specifies that each unit must
implement two error counters: one for transmit-errors and the other for receive-errors.

These counters work under a rather complex algorithm. In short, their counts increase
when errors are detected and decrease on successful message transfers. When the
CAN devices are reset they begin to operate in Error Active mode. As errors begin to
occur, the error count increases and eventually they reach a threshold beyond which
the node enters the Error Passive state. If the errors persist, the error counts will keep
increasing until the node shuts itself off, entering the Bus-Off state.
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4.8 CAN Hardware Implementations
➢ When implementing any kind of device that communicates via CAN, the
designer does not need to be concerned with the CAN communication itself.

➢ All the functionality required to handle a CAN message is implemented in the
hardware. These CAN hardware implementations are commonly called CAN
Controllers.
➢
All that is required from the designer is:

➢ Basic knowledge of how the CAN protocol works.
➢ Implementation of the hardware interface between the CAN controller and the
CAN bus (possibly also between the CAN controller and the microprocessor).
➢ Ability to program the CAN controller according to the needs of the application.

For this reason, this section will deal with hardware implementation issues

4.8.1 CAN Controller Organisation
➢ There are different ways in which the CAN protocol may be implemented in the various
CAN controllers available on the market.

➢ The type of communication that can be achieved is identical for all implementations.
However, there are differences regarding the extent to which the controller takes over
message handling.



















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All CAN controllers share a common structure such as the one shown in Figure 4.14.

CPU Data and
Address Bus
Message
Memory Buffer
CPU Interface
Logic
Transceiver Control Logic
Bit Stream
Processor
Error
Management
Logic
Bit Timing
Logic
Clock
Generator
Oscillator
Output Driver Logic Input Driver Logic


Figure 4.14. Typical structure of a CAN controller
The functional blocks perform the following tasks:

The CPU Interface Logic (CIL)

• Executes commands from the processor running the software and controls data transfers
on the CAN serial bus. Global status and control registers as well as the control bits in
the communication objects are used primarily by the CPU interface logic.

The Message Buffer Memory

• Stores individual CAN objects for transmission or reception. The CPU communicates
only with this area in order to transmit and receive messages. The CPU Interface Logic
manages the data exchange.

The Bit Stream Processor (BSP)

• Controls the data stream between the message buffer memory (parallel data) and the
bus line (serial data). It controls the entire protocol, differentiates between the frame
types and detects frame errors.

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The Error Management Logic

• Receives error messages from the bit stream processor and, in turn, sends back
information about the Error State to the bit stream processor and the CPU Interface
Logic.

The Clock Generator

• Simply used to derive a suitable clock frequency for the CAN controller based on the
frequency of an external clock oscillator.

The Bit Timing Logic (BTL)

• Determines the timing of the bits and maintains the CAN controller synchronised
with the edges of the bit stream on the CAN bus. It monitors the bus through a
differential input comparator and determines the bit timings related to the serial bus.
The BTL synchronises on a transition at the start of the frame and re-synchronises on
further transitions during reception of the frame. The BTL also provides programmable
time segments to compensate for the propagation delay times and phase shifts.

The Transceiver Control Logic (TCL)

• Consists of bit stuffing logic, programmable output driver logic, CRC logic and
data shift registers. The BSP co-ordinates these individual elements. Reception,
arbitration, transmission and error signalling are performed by the TCL.


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4.8.2 Basic CAN vs Full CAN Implementations
With respect to Message filtering, two broad categories of CAN implementation can
be specified - Basic CAN and Full CAN implementation. The distinction between the
two is becoming less and less important. This is mainly because most of the newer
Full CAN controllers also provide the functionality of Basic CAN.

Full Can Implementation

➢ In Full CAN controllers, individual sections or objects of the message buffer
memory are reserved for the transmission or reception of CAN frames with pre-
set programmable identifiers.

Incoming Message ID=401 ID=401
ID=501
Incoming Message
Incoming Message
ID=545
ID=612
Incoming Message
Incoming Message
No ID Match with any object,
message is rejected
ID Match, store message in
this object
Notify CPU


Incoming Message ID=401
Incoming Message ID=545
ID=401
ID=501
Incoming Message
Incoming Message
ID=545
ID=612
Incoming Message
Incoming Message
No ID Match with any object,
message is rejected
ID Match, store message in
this object
Notify CPU

Figure 4.15: Principles of Full CAN operation: ID match

➢ If the identifier matches the one programmed into the header of the object, the
data is stored in that object or memory area.


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Incoming Message ID=401
Incoming Message ID=545
ID=401
ID=501
Incoming Message
Incoming Message
ID=545
ID=612
Incoming Message
Incoming Message
No ID Match with any object,
message is rejected
Incoming Message ID=601

Figure 4.16: Principles of Full CAN operation: No ID match

➢ If the identifier does not match any of the programmed object identifiers, the
data is rejected by the hardware.

This type of arrangement can save the designer a great deal of trouble when writing
the CAN software.

Basic CAN Implementation

➢ In Basic CAN, the controller receives all messages irrespective of their
identifier.
➢ Messages are put into a ‘receive message buffer’.
➢ It is then up to the processor collecting the incoming messages to accept or
reject these messages.
➢ Therefore, a software routine must be invoked every time a CAN message is
received, regardless of whether the message is intended for the application or
not.
➢ This adds a large amount of software and processing overhead for an
application.

Software filtering

➢ Software filtering can be used to help reduce the high processing overhead in
Basic CAN implementations.
➢ Here, it is possible to configure the controller to accept the whole, or subset of
the CAN identifier range.


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For example, In the Philips 8x592 microcontroller and the Motorola 68HC05X family
of microcontrollers, the filter consists of an Acceptance Mask (AM) register and an
Acceptance Code (AC) register.

ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
Message Identifier (ID)
Acceptance Mask (AM)
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Acceptance Code (AC)

Figure 4.17: Basic CAN acceptance filtering registers
Consider Figure 4.17:

➢ The Acceptance Mask and Acceptance Code register are 8 bits long
➢ The filtering is based on the top 8 bits of the CAN identifier
➢ The acceptance mask register defines whether the corresponding bits in the
Acceptance Code register and the CAN identifier must match to pass the
acceptance test
➢ This is done by setting the must-match bits in the Acceptance Mask to zero.
4.8.2.1 Example
Consider Figure 4.18.

➢ Consider the following two Identifiers:

ID1 = 01111111001

ID2 = 01110101011

➢ Let the Acceptance Code be 01110111 in binary.
➢ Let the Acceptance Mask be 00000010 in binary.

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➢ All logic-zero bits in the Acceptance Mask are set to must-match; all logic-one
bits are set to don’t-care.

0 1 1 1 1 1 1 1 0 0 1
0 0 0 0 0 0 1 0
ID1
Acceptance Mask
0 1 1 1 0 1 1 1
Acceptance Code
Mask ‘don’t-care’
Mask mis-match


0 1 1 1 0 1 0 1 0 1 1
ID2
0 0 0 0 0 0 1 0
Acceptance Mask
0 1 1 1 0 1 1 1
Acceptance Code
ID bits
ignored
Mask ‘don’t-care’


Figure 4.18: Example: Basic CAN acceptance test

➢ In this situation, ID1 fails the acceptance test whilst ID2 passes.
➢ Based on this example, a range of identifiers from 952 to 959 decimal will pass
the filtering test of the CAN controller.
➢ Obviously, the software must perform further filtering if only some of these
messages are to be accepted.
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4.8.2.2 Example 2
Consider the following Identifiers:

ID1 = 01111111001 ID2 = 01110101011
ID3 = 01000111001 ID4 = 00011111111

➢ Let the Acceptance Code be 01001101 in binary.
➢ Let the Acceptance Mask be 00011010 in binary.

Which Messages will pass the acceptance test?

ID
Acceptance Mask
Acceptance Code



ID
Acceptance Mask
Acceptance Code



ID
Acceptance Mask
Acceptance Code


ID
Acceptance Mask
Acceptance Code


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4.9 Stand-alone versus Embedded CAN Controllers
Regarding the way in which a CAN controller may be integrated into a product, a
distinction needs to be made between stand-alone CAN controllers and embedded
CAN controllers.

➢ Stand-alone CAN controllers are CAN hardware implementations
encapsulated in one physical integrated circuit. Example: SJA1000 chip from
Philips.

➢ Embedded CAN controllers are CAN hardware implementations that are
provided as an additional embedded peripheral within a microcontroller.
Example: C167 chip from Siemens.
➢

Microcontroller
Standalone CAN
Controller
Bus Driver
Microcontroller
Integrated CAN
Controller
Bus Driver
TxD RxD Tx1 Tx0
Rx1 Rx0
External
Data Bus
External
Address Bus






Figure 4.19: Variants of CAN hardware
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4.9.1 Overview of the CAN Hardware Market
➢ It is important to transmit to the reader the idea that the range of CAN hardware
products available on the market is broad.

➢ This is true for both transceivers and CAN controllers, but more so for the latter.

Consider Table 4.3 and Table 4.4. Table 4.3 shows that a number of different
manufacturers produce bus driver or transceiver chips

Part Number Max Speed Manufacturer
SN75LBC031D 500 Kbit/sec Texas Instruments
UC5350 1 Mbit/sec Unitrode
82C250, 82C251 1 Mbit/sec Philips Semiconductors
Table 4.3: A selection of transceiver chips
Table 4.4 shows a list of some of the integrated and standalone CAN controllers
available. This is by no means an exhaustive list and many other variants exist (the
same should be noted for Table 4.3).

Part Number Extended
ID
Microcontro
ller
Manufacturer
FM2C Yes 16-bit Fujitsu
H8/300H Yes 16-bit Hitachi
AN 82527 Yes None Intel
AN87C196CA Yes 16-bit Intel
68HC05X4 No 8-bit Motorola
M37630 E4/M4 Yes 8-bit Mitsubishi
COP684BC Passive 8-bit National Semiconductors
PD70F3xxx Yes 32-bit NEC
P8X592/8 No 8-bit Philips
ST10F167 Yes 16-bit SGS Thompson
SAE81C90/91 Passive None Siemens
C167CR Yes 16-bit Siemens
TMP88PP87 Yes 8-bit Toshiba
TCG54AF Yes None Toshiba

Table 4.4: Standalone and integrated CAN controllers
➢ Most of the manufacturers listed here produce more than one CAN product.
➢ Note that most of these CAN controllers support the extended 29-bit identifier
range although some only support 29-bit identifiers passively.
➢ This means they can be used on the same network as CAN controllers using
the extended 29-bit ID but they use standard 11-bit identifiers only

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4.10 CANopen
4.10.1 Re-look at the CAN ISO/OSI Reference Model.
Application Layer 7
Presentation Layer 6
Session Layer 5
Transport Layer 4
Network Layer 3
Data Layer 2
Physical Layer 1
ISO/OSI Reference Model
CAN Data Link Layer
(CAN specification 2.0)
CAN Physical Layer
(ISO11898)
CAN Protocol
Application Layer
(CANopen)

Figure 4.20: The CAN protocol and the ISO/OSI Reference Model
Once again, let us consider the CAN specification in relation to the 7 layer ISO/OSI
Reference Model. As shown by Figure 4.20, the CAN specification is mapped onto the
lower two layer of the ISO/OSI reference model – Physical Layer and Data Link Layer.

➢ The can Data Link Layer offers services for transferring and requesting data
units no longer than 8 bytes.

➢ This is sufficient for simple applications, as CAN was initially intended.
However, in more complex distributed application, additional functionality is
required – this might involve the co-ordination or initialisation of many nodes,
or the transmission of blocks of data longer than 8 bytes.

➢ In order to achieve this, in terms of the ISO/OSI model, higher layer services
are needed.

It is for this reason that the CAN in Automation (CiA) organisation specified a CAN
reference model, and within it, the CAN Application Layer (CAL). CAL is now widely
accepted as the standard top protocol layer in CAN based systems. CAL is widely
used in application fields such as traffic control and medical fields.
4.10.2 Missing Layers
Before considering the Application Layer, we will outline the reasons for omitting the
other layers in the ISO/OSI reference model.


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Network Layer

➢ The Network Layer is supposed to handle the interconnection of several
networks. Inter-networking never happens in CAN. Therefore, these services
are not required.

Transport Layer

➢ The purpose of this layer is to guarantee the reliable transfer of messages of
arbitrary length over potentially unreliable networks. CAN fieldbus is sufficiently
reliable to not need this service.

➢ Furthermore, in real time systems, if a transfer fails, the data is unlikely to be
valid at a later time, so we would not want to repeatedly try to transmit data over
a long period of time.

Session Layer

➢ In real time applications, the concept of a session is meaningless. The control
system runs continuously. Therefore, the services offered by the Session layer
are not applicable.

Presentation Layer

➢ The presentation layer basically deals with the encoding of the data and
keeping track of its meaning across the network.

➢ In CAN, a basic set of data types are already defined and must be used by all
applications to describe their data.

➢ Furthermore, CAN assumes that the meaning of the data is known by all
applications beforehand. Therefore, the functionality of the Presentation Layer
is not required.

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4.10.3 CAN Application Layer
CAN Application Layer
CMS NMT DBT LMT

Figure 4.21: CAN Application Layer
The CAN application Layer provides a large number of services, which are divided into
four application layer entities. These entities are as follows:

CAN based Message Specification (CMS)

➢ Offers an open, object orientated environment in which to design user
applications

➢ It is a programming language used to specify what Communication Objects
(COBs) a module uses and how they are formatted. It can also describe all
CAN Data Link Layer Features.

*COBs – messages with a particular message identifier.

Network Management (NMT)

➢ Offers an open, object orientated environment in which one module (NMT
master) is able to deal with the initialisation and possible failures of other nodes
(NMT slaves).

➢ The NMT entity provides the basic tools for the construction and maintenance
of the distributed application.

Distributor (DBT)

➢ In CAN, the identifier field determines the message priority of a module. For this
reason, the CAN module manufacturer cannot fix the value of the identifier.
Instead, the system designer must take control over the priority system.

➢ The Distributor entity handles the allocation of message identifiers (COBs) and
thus the priority system.

➢ The DBT offers a mechanism for dynamic distribution of identifiers by one
module (DBT master) to the other nodes (DBT slaves)


Layer Management (LMT)

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➢ Offers the possibility to let a Layer Management Master node control the
settings of certain layer parameters in other modules, called LMT Slaves

Usually, the master functionality of NMT, DBT and LMT will be centred on one
device that controls the operation of the network. However, this is not
mandatory, and functions can be performed by different devices.


4.10.4 CANopen Profiles
A very important concept in CANopen is that of profiles. These profiles can be divided
into two categories.

i) CANopen device profiles
ii) CANopen communication profiles

i) CANopen device profiles
CANopen device profiles describe the functionality of a device. A device profile
simply defines a standard device. This standard device has basic properties which
every device in its class must exhibit.

➢ Device profiles provide room for additional optional functionality.

➢ Device profiles also provide for manufacturer specific functionality so
manufacturers can implement functionality not covered by the standard profiles.

Example: CAN in Automation (CiA) have produced a family of standard device
profiles: -

• DS401 Low level I/O analogue and digital.
• DSP402 Drives, servo, inverter and stepper.
• DSP406 Encoder absolute and relative
• DSP401 Low level sensor
• WD402 Drives
• WD404 Measuring devices
• WD405 Programmable devices
• WD406 Encoders
• WD407 Public transport

Special interest groups are always working on new device profiles, which
have yet to be covered.
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ii) CANopen communication profile
➢ CANopen communication profiles describe how subsets of the CAN application
layer services are used by the device. CANopen communication profiles
define how the device is expected to behave when communicating.
➢ The CANopen specification divides the Application Layer functionality into
several Service Objects. Each Service Object provides specific
functionality, and all the services related to it.
➢ When an application initiates a CANopen service to communicate with a remote
CANopen device, the Service Object offering the referred service will interact
with a peer Service Object on the remote CANopen node to carry out the data
exchange.
➢ When an application initiates a CANopen service to communicate with a remote
CANopen device, the Service Object offering the referred service will interact
with a peer Service Object on the remote CANopen node to carry out the data
exchange.

Application A Application B
CAN
Service
Object
Service
Object
Application
Layer
Application
Layer

Figure 4.22: CANopen Service Objects

4.10.5 4 Service primitives
Request
➢ Issued by an application to the Application Layer to request a service
Indication
➢ Issued by the Application Layer to the application to report that a network event
has occurred, or that a service is required from the application by another node
Response
➢ Issued by the application to the Application Layer as a reply to an indication
Confirmation
➢ Issued by the Application Layer to the application to report on the result of a
previous request.
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4.10.6 Application Layer services
Based on these service primitives, the Application Layer services in CANopen can be
classified as follows:

Local Service
Application Layer
Application A
Request

Figure 4.23: Principle of Local Service

➢ Only a Request is used. The application triggers a local network event

Provider Initiated Service
Application Layer
Application A
Indication

Figure 4.24: Principle of Local Provider Initiated Service

➢ Only an Indication is used. This signals to the application that a local network
event has occurred.

Unconfirmed Service
Application Layer
Application A
Request
Application Layer
Application B
Indication

Figure 4.25: Principle of Unconfirmed Service

➢ An application produces a Request, which then requires an Indication to be
given to the application running on another node

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Confirmed Service
Application Layer
Application A
Request
Application Layer
Application B
Indication


Figure 4.26: Principle of Confirmed Service

➢ The same process to the Unconfirmed Service, but a Response is then issued
by the remote application. This response is signalled to the local application in
the form of a Confirmation primitive.


As mentioned previously, when messages are sent across the CAN network each
node must decide whether or not the data is relevant to that node. This is achieved by
comparing the message identifier to a list of acceptable identifiers contained in the
memory buffer (Full CAN) of the node, or via software filtering and checking (Basic
CAN). This mechanism makes CAN a highly flexible system in which several types of
communication mechanism can be implemented. This is reflected in the diversity of
communication relationships that can co-exist in the network, involving two or more
devices.

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These relationships all belong to one of three basic types of communication model:

(1) Master/Slave

➢ Here, one device (the Master) is responsible for co-ordinating some aspect of
the operation of the network and communicating with other devices in the
network (the Slaves)
➢ The services offered by CANopen, at the Application Layer level, based on
Master/Slave operation are related to network management mechanisms.

These services can be confirmed, or unconfirmed. See Figure 4.27.
Master
Data Frame
Slave
indication
indication
indication

Unconfirmed service
Master
Data Frame
Slave
indication
response
Remote Frame
confirmation
request

Confirmed service

Figure 4.27: Master/Slave Communication

(2) Client/Server

➢ Client/Server relationships only involve two devices. It is a peer-to-peer
interaction in which one device (the Client) reads data from, or writes data to,
another device (the Server)
➢ The services offered by CANopen, at the Application Layer level, based on
Client/Server operation are typically used for off-line device
configuration.

These services are always confirmed where the Client issues a request to
download or upload data and the server is expected to give a response indicating
the result of the operation

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Client
Data Frame
Server
indication
responseconfirmation
request
Data Frame

Figure 4.28: Client/Server Communication

(3) Producer/Consumer

➢ Here, one device is said to be the producer of a piece of data that it wants to
transmit onto the bus. There may be any number of devices on the network that
pick up this data whenever it is transmitted. The receiving devices are called
Consumers.
➢ The services offered by CANopen, at the Application Layer level, based on
Producer/Consumer communication are typically real time exchange of
process data

These services can be unconfirmed (Push Model), or confirmed (Pull model), as
shown in Figure 4.29.


Producer
Data Frame
Consumer
indication
indication
indication
Push Model

Producer
Data Frame
Consumer
request
confirmation
Remote Frame
response
indication
Pull Model
request
indication
indication

Figure 4.29: Producer/Consumer Communication

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4.10.7 Device Definition: The Object Dictionary
CANopen uses an object orientated approach to the definition of standard devices.
The CANopen model of a device is shown in Figure 4.30.

➢ Each device is represented as a set of objects that can be accessed through
the network.
➢ An object is simply a combination of commands and/or data relevant to
the operation of a device. Every aspect of the operation of a device is
mapped onto one or more of these objects.
➢ It is therefore possible to change the configuration or the status of a
device simply by using the network to alter the attributes of a particular
object within it.

Communication
Object
Application
Object
Application
Object
Object
Dictionary
P
ro
ce
ss
C
A
N
Application
Object
Application
Object
Communication
Object
Communication
Object
Communication Profile Device Profile
Figure 4.30: CANopen device model showing communication and application objects
From the diagram we can define two types of objects:

Communication Objects

➢ These objects represent a communication specific functionality within the
device. They are specified in the CANopen Communication profile.
Application Objects

➢ These objects represent device specific functionality – such as the state of
an input digital signal. They are specified in the CANopen Device profile

All the objects in a device can be accessed through an object dictionary where they
are represented.

➢ The object dictionary is the most important part of a device profile. The object
dictionary is a map to the internal structure of a device.
➢ If the structure of the object dictionary is known, then everything to implement
a distributed application using this device is also known.
i) Object Dictionary Structure
➢ Objects may be more than just values and may be arrays or structures (records)
of data. They have attributes such as const, read-only, write-only, read-
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write. The attribute const represents an object which is not changeable via
normal communication with the device or by the device itself. A read-only
attribute is used for objects which may be read but not written, a write-only
attribute can be written to but not read and an object with read-write attribute
can be read from or written to.
➢ CANopen services give the user full access to the object dictionary in a
device for read or write.
➢ Objects are stored in the Object Dictionary according to their function. Index
ranges are reserved for specific function groups, as shown in Table 4.5.

Index Object
0000 Not Used
0001h - 009Fh Data Type Definitions
00A0h - 0FFFh Reserved
1000h - 1FFFh Communication Parameters
2000h - 5FFFh Manufacturer Specific Parameters
6000h - 9FFFh Profile Specific Parameters
A000h - FFFFh Reserved
Table 4.5: Object Dictionary organisation
ii) Object Dictionary Addressing
➢ Objects are addressed by the use of a 16 bit index and an 8 bit sub
index.

The way the sub index is used varies with the type of object.

➢ A simple object consisting of a single value exists at sub index 0.
➢ For arrays and structures the sub index references the number of elements, for
strings it references the number of characters in the string.
➢ With devices of more than one channel it is used as a reference to the channel.
➢ For example, an analogue input device with four analogue inputs would have
the value 4 in sub index 0. Sub index 2 would reference channel 2 and so on

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Index Sub-
Index
Object Name Type Attribute Default
Value
1001h 00 VAR Error Register U8 ro 00h
1400h Record
VAR
VAR
VAR
1st Receive PDO
No. of entries
PDO COB-ID
PDO Type

U8
U32
U8

ro
rw
rw

02h

FFh
00A0h -
0FFFh

00
01
02
03
04
Array
VAR
VAR
VAR
VAR
VAR
R_Analogue_In
No. of Channels
Channel_1
Channel_2
Channel_3
Channel_4

U8
Float
Float
Float
Float

ro
ro
ro
ro
ro

04h

….. …… ….. …..
Table 4.6: Example Object Dictionary Structure
4.10.8 Communication Types
There are four communication types used in CANopen.
➢ Service Data Object (SDO) transfer - configuration of devices.
➢ Process Data Object (PDO) transfer - transfer of application data.
➢ Network Management and Administration - application co-ordination.
➢ Predefined format messages - device synchronisation and data transfer

At the very least a device must support SDO transfers to be CANopen compatible. A
device may support multiple PDO messages with (perhaps) different fixed mappings
for each message. The mapping for each individual PDO message is stored in the
devices object dictionary (for both transmit and receive PDOs). Table 4.7 shows the
fundamental difference between SDO and PDO message transfers:

➢ To summarise, PDOs may be thought of as a method of fast small load
transportation and SDOs as larger load but slower transportation.

Service Data Object
(SDO)Communication
Service Data Object
(SDO)Communication
Low Priority high volume data transfers High Priority Low volume data
transfers
Uses 16 bit index, 8 bit sub index object
addressing structure
Objects mapped onto individual bytes
of the data field
Data transfers greater than 8 bytes of data
using multiple CAN messages via CMS
Data transfers up to 8 bytes of data
using a single CAN messages
Table 4.7: Message Communication: SDO versus PDO